《计算机应用》唯一官方网站 ›› 2022, Vol. 42 ›› Issue (5): 1524-1530.DOI: 10.11772/j.issn.1001-9081.2021030460

• 先进计算 • 上一篇    下一篇

基于阵列处理器的最小均方误差检测算法并行设计与实现

刘帅1, 蒋林2(), 李远成2, 山蕊3, 朱育琳4, 王欣4   

  1. 1.西安科技大学 通信与信息工程学院, 西安 710054
    2.西安科技大学 计算机科学与技术学院, 西安 710054
    3.西安邮电大学 电子工程学院, 西安 710121
    4.西安科技大学 电气与控制工程学院, 西安 710054
  • 收稿日期:2021-03-26 修回日期:2021-06-25 接受日期:2021-06-28 发布日期:2022-06-11 出版日期:2022-05-10
  • 通讯作者: 蒋林
  • 作者简介:刘帅(1998—),男,陕西延安人,硕士研究生,主要研究方向:计算机体系结构
    蒋林(1970—),男,陕西杨凌人,教授,博士,主要研究方向:专用集成电路设计、计算机体系结构、计算机图形图像处理 jianglin@xust.edu.cn
    李远成(1981—),男,河南开封人,讲师,博士,CCF会员,主要研究方向:计算机体系结构、并行计算、机器学习
    山蕊(1986—),女,陕西咸阳人,副教授,博士,主要研究方向:集成电路设计
    朱育琳(1996—),女,陕西西安人,硕士研究生,主要研究方向:计算机体系结构
    王欣(1995—),女,陕西咸阳人,硕士研究生,主要研究方向:可重构存储结构。
  • 基金资助:
    国家自然科学基金资助项目(61834005);陕西省自然科学基金资助项目(2020JM?525)

Parallel design and implementation of minimum mean square error detection algorithm based on array processor

Shuai LIU1, Lin JIANG2(), Yuancheng LI2, Rui SHAN3, Yulin ZHU4, Xin WANG4   

  1. 1.College of Communication and Information Engineering,Xi’an University of Science and Technology,Xi’an Shaanxi 710054 China
    2.College of Computer Science and Technology,Xi’an University of Science and Technology,Xi’an Shaanxi 710054,China
    3.School of Electronic Engineering,Xi’an University of Posts and Telecommunications,Xi’an Shaanxi 710121,China
    4.College of Electrical and Control Engineering,Xi’an University of Science and Technology,Xi’an Shaanxi 710054,China
  • Received:2021-03-26 Revised:2021-06-25 Accepted:2021-06-28 Online:2022-06-11 Published:2022-05-10
  • Contact: Lin JIANG
  • About author:LIU Shuai, born in 1998,M. S. candidate. His research interestsinclude computer architecture.
    JIANG Lin, born in 1970, Ph. D., professor. His researchinterests include application specific integrated circuit design,computer architecture,computer graphics and image processing.
    LI Yuancheng, born in 1981,Ph. D.,lecturer. His researchinterests include computer architecture,parallel computing,machine learning.
    SHAN Rui, born in 1986, Ph. D., associate professor. Herresearch interests include integrated circuit design.
    ZHU Yulin, born in 1996,M. S. candidate. Her research interestsinclude computer architecture.
    WANG Xin, born in 1995,M. S. candidate. Her research interestsinclude reconfigurable storage structure.
  • Supported by:
    National Natural Science Foundation of China(61834005);Natural Science Foundation of Shaanxi Province(2020JM-525)

摘要:

针对大规模多输入多输出(MIMO)系统中,最小均方误差(MMSE)检测算法在可重构阵列结构上适应性差、计算复杂度高和运算效率低的问题,基于项目组开发的可重构阵列处理器,提出了一种基于MMSE算法的并行映射方法。首先,利用Gram矩阵计算时较为简单的数据依赖关系,设计时间上和空间上可以高度并行的流水线加速方案;其次,根据MMSE算法中Gram矩阵计算和匹配滤波计算模块相对独立的特点,设计模块化并行映射方案;最后,基于Xilinx Virtex-6开发板对映射方案进行实现并统计其性能。实验结果表明,该方法在MIMO规模为128×4128×8128×16的正交相移键控(QPSK)上行链路中,加速比分别2.80、4.04和5.57;在128×16的大规模MIMO系统中,可重构阵列处理器比专用硬件减少了42.6%的资源消耗。

关键词: 大规模多输入多输出, 最小均方误差算法, 并行映射, 阵列处理器, 可重构

Abstract:

In massive Multiple-Input Multiple-Output (MIMO) systems, Minimum Mean Square Error (MMSE) detection algorithm has the problems of poor adaptability, high computational complexity and low efficiency on the reconfigurable array structure. Based on the reconfigurable array processor developed by the project team, a parallel mapping method based on MMSE algorithm was proposed. Firstly, a pipeline acceleration scheme which could be highly parallel in time and space was designed based on the relatively simple data dependency of Gram matrix calculation. Secondly, according to the relatively independent characteristic of Gram matrix calculation and matched filter calculation module in MMSE algorithm, a modular parallel mapping scheme was designed. Finally, the mapping scheme was implemented based on Xilinx Virtex-6 development board, and the statistics of its performance were performed. Experimental results show that, the proposed method achieves the acceleration ratio of 2.80, 4.04 and 5.57 in Quadrature Phase Shift Keying (QPSK) uplink with the MIMO scale of 128×4128×8 and 128×16, respectively, and the reconfigurable array processor reduces the resource consumption by 42.6% compared with the dedicated hardware in the 128×16 massive MIMO system.

Key words: massive Multiple-Input Multiple-Output (MIMO), Minimum Mean Square Error (MMSE) algorithm, parallel mapping, array processor, reconfigurable

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