计算机应用 ›› 2012, Vol. 32 ›› Issue (11): 3259-3261.DOI: 10.3724/SP.J.1087.2012.03259

• 典型应用 • 上一篇    下一篇

基于FPGA的高速采样缓存系统的设计与实现

郑争兵   

  1. 陕西理工学院 物理与电信工程学院,陕西 汉中723003
  • 收稿日期:2012-05-07 修回日期:2012-06-19 发布日期:2012-11-12 出版日期:2012-11-01
  • 通讯作者: 郑争兵
  • 作者简介: 郑争兵(1980-),男,湖北黄冈人,讲师,硕士,主要研究方向:嵌入式系统。
  • 基金资助:
    校级科研项目

Design and implementation of high-speed sampling buffer system based on FPGA

ZHENG Zheng-bing   

  1. School of Physics and Telecommunication Engineering, Shaanxi University of Technology, Hanzhong Shaanxi 723003, China
  • Received:2012-05-07 Revised:2012-06-19 Online:2012-11-12 Published:2012-11-01
  • Contact: ZHENG Zheng-bing

摘要: 为了提高高速数据采集系统的实时性,提出一种基于FPGA+DSP的嵌入式通用硬件结构。在该结构中,利用FPGA设计一种新型的高速采样缓存器作为高速A/D和高性能DSP之间数据通道,实现高速数据流的分流和降速。高速采样缓存器采用QuartusⅡ9.0 软件提供的软核双时钟FIFO构成乒乓操作结构,在DSP的外部存储器接口(EMIFA)接口的控制下,完成高速A/D的数据流的写入和读出。测试结果表明:在读写时钟相差较大的情况下,高速采样缓存器可以节省读取A/D采样数据时间,为DSP提供充足的信号处理时间,提高了整个系统的实时性能。

关键词: 双时钟先进先出, 现场可编程门阵列, 高速采样, 乒乓操作, 外部存储器接口

Abstract: An embedded general-purpose hardware structure based on FPGA + DSP was proposed in order to improve the real-time performance of the high-speed data acquisition system. In the structure, a new high speed sampling buffer as the data channel between the high-speed A/D and DSP was designed in FPGA and was used to realize the diversion and deceleration of high-speed data stream. The high-speed sampling buffer was based on the ping-pong operation structure of soft-core dual-clock First In First Out (FIFO) provided by Quartus Ⅱ 9.0. Under the control of the External Memory Interface A (EMIFA) interface of the DSP, it completed write-and-read operations of high-speed A/D data streams. The test results indicate that: in the case of large difference between the value of the read-and-write clock, high speed sampling buffer can save the time of the A/D sampling data to provide sufficient signal processing time for DSP, so the real-time performance of the entire system is improved. high speed sampling buffer can save the time of the A/D sampling data to provide sufficient signal processing time for DSP ,so the real-time performance of the entire system is improved.

Key words: dual-clock First In First Out (FIFO), Field-Programmable Gate Array (FPGA), high-speed sampli

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