计算机应用 ›› 2013, Vol. 33 ›› Issue (03): 756-758.DOI: 10.3724/SP.J.1087.2013.00756

• 信息安全 • 上一篇    下一篇

基于FPGA的数字水印提取系统的设计

王沙沙*,高飞,温英新,于静   

  1. 北京理工大学 信息与电子学院,北京 100081
  • 收稿日期:2012-09-04 修回日期:2012-10-31 出版日期:2013-03-01 发布日期:2013-03-01
  • 通讯作者: 王沙沙
  • 作者简介:王沙沙(1987-),女,山东潍坊人,硕士研究生,主要研究方向:数字水印、FPGA设计; 高飞(1959-),女,北京人,教授,博士生导师,主要研究方向:数字水印、无线通信、数字图像处理; 温英新(1986-),男,河北沧州人,硕士研究生,主要研究方向:数字水印、嵌入式系统; 于静(1987-),女,内蒙古通辽人,硕士研究生,主要研究方向:数字水印、DSP软件设计。

Design of digital watermark extraction system based on FPGA

WANG Shasha*, GAO Fei, WEN Yingxin, YU Jing   

  1. School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, China
  • Received:2012-09-04 Revised:2012-10-31 Online:2013-03-01 Published:2013-03-01

摘要: 针对传统软件实现数字水印系统难以满足实时性的问题,提出了基于现场可编程门阵列(FPGA)的硬件实现方案。通过对数字水印提取系统进行深入研究,设计了易于FPGA实现的数字水印算法和适用于5/3小波变换的算法结构,并进一步设计出与算法相对应的新的水印提取结构。该结构体现了流水线和高度并行性,计算效率高,具有体积小、功耗低、实时性强等特点。经仿真验证证实了所设计系统的正确性,算法结构具有广泛的适用性。

关键词: 数字水印提取, 现场可编程门阵列, 5/3小波变换, 流水线, 并行

Abstract: To solve the problem that software implementation cannot meet real-time requirements, a hardware scheme based on Field-Programmable Gate Array (FPGA) was presented. By analyzing the digital watermark extraction system, a watermark-embedding algorithm suitable for FPGA implementation was designed and its structure is applicable to 5/3 wavelet transform. Moreover, a new watermark extraction structure that corresponded to the embedding algorithm was also proposed. The pipeline and highly parallel structure has the features of high computation efficiency, small size, low-power and real-time process. The simulation results demonstrate the system's correctness and the algorithm's abroad applicability.

Key words: digital watermark extraction, Field-Programmable Gate Array (FPGA), 5/3 wavelet transform, pipeline, parallelism

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