关键词: 片上多核处理器, 二级缓存, 动态划分, 低功耗, 性能

Abstract: This paper proposed a Low-Power oriented cache Design (LPD) of Level 2 (L2) cache for multi-core processors. LPD considered three different ways to reduce the power consumption while promising the best performance: Low Power oriented Hybrid cache Partition algorithm (LPHP), Cache Reconfiguration Algorithm (CRA), and Way-Prediction based on L2 cache Partition algorithm (WPP-L2). LPHP and CRA closed the columns that were not in use dynamically. WPP-L2 predicted one appropriate way before cache accesses, which could save the access time, so as to save power. These three methods of LPD saved power consumption by 20.5%, 17% and 64.6% on average over the traditional Least Recently Used (LRU) strategy with improvement of the throughput and little influence on the runtime of programs. The experimental results show that this method can reduce the power of multi-core processors significantly and maintain the system performance.

Key words: Chip Multi-core Processor (CMP), Level 2 (L2) cache, dynamic partition, low power, performance