基于高层次综合的AES算法研究与设计

doi:10.11772/j.issn.1001-9081.2017.05.1341

计算机应用 ›› 2017, Vol. 37 ›› Issue (5): 1341-1346.DOI: 10.11772/j.issn.1001-9081.2017.05.1341

基于高层次综合的AES算法研究与设计

张望^1,2, 贾佳³, 孟渊^1,2, 白旭^1,2

1. 中国科学院信息工程研究所, 北京 100093;
2. 信息内容安全技术国家工程实验室, 北京 100093;
3. 北京特种工程设计研究院, 北京 100028

收稿日期:2016-09-12 修回日期:2016-11-27 出版日期:2017-05-10 发布日期:2017-05-16
通讯作者: 张望
作者简介:张望(1992-),男,江西南昌人,博士研究生,主要研究方向:信息安全、计算机体系结构;贾佳(1981-),男,北京人,工程师,博士,主要研究方向:通信与信息工程;孟渊(1983-),男,甘肃高台人,硕士研究生,主要研究方向:信息安全;白旭(1990-),男,辽宁喀左人,博士研究生,主要研究方向:信息安全、计算机体系结构。
基金资助:
国家自然科学基金青年科学基金资助项目（61402475）；新疆自治区科技专项（201230123）。

Research and design of AES algorithm based on high-level synthesis

ZHANG Wang^1,2, JIA Jia³, MENG Yuan^1,2, BAI Xu^1,2

1. Institute of Information Engineering, Chinese Academy of Sciences, Beijing 100093, China;
2. National Engineering Laboratory of Information Security Technologies, Beijing 100093, China;
3. Beijing Special Engineering Design and Research Institute, Beijing 100028, China

Received:2016-09-12 Revised:2016-11-27 Online:2017-05-10 Published:2017-05-16
Supported by:
This work is partially suuported by the Youth Science Fund of National Natural Science Foundation of China (61402475), the Xinjiang Uygur Autonomous Region Science and Technology Project (201230123).

摘要/Abstract

摘要： 由于对广泛使用的AES算法的性能要求越来越高，基于软件的密码算法已经越来越难以满足高吞吐量密码破解的需求，因此越来越多的算法利用现场可编程逻辑门阵列（FPGA）平台进行加速。针对AES算法在FPGA硬件上存在的开发复杂度高且开发周期长等问题，采用高层次综合（HLS）设计方法，使用高级程序语言描述并设计AES硬件加速算法。首先利用循环展开等提高运算并行度；其次使用资源平衡技术进行优化，充分利用片上存储和电路资源；最后添加全流水结构，提高整体设计的时钟频率和吞吐量，同时也详细对比分析基准设计、利用结构展开、资源均衡以及流水线优化方法的设计。经过实验表明，在Xilinx xc7z020clg484 FPGA芯片上，最终AES算法的时钟频率最高达到127.06 MHz，而吞吐量达到了16.26 Gb/s，较之基准的AES设计，性能提升了三个数量级。

关键词: 对称密钥加密算法, 高级加密标准, 高层次综合, 现场可编程逻辑门阵列

Abstract: Due to the increasingly high performance requirements on the Advanced Encryption Standard (AES) algorithm which was widely used, software-based cryptographic algorithms have been increasingly difficult to meet the demands of high-throughput ciper cracking. As a result, more and more encryption algorithms have been accelerated by using Field-Programmable Gate Array (FPGA) platform. Focused on the issue that the development of AES algorithm based on FPGA has high complexity and long development cycle, with High-Level Synthesis (HLS) design methodologies, AES hardware acceleration algorithm was designed by using high-level programming language. Firstly, loop unrolling, etc were used to improve operation parallelism. Secondly, to make full use of on-chip memory and circuit resources, the resource balance optimization technology was used. Finally, the full pipeline structure was added to improve the clock frequency and throughput of the overall design. The detailed analysis and comparison of the benchmark design and different optimized designs with structural expansion, resource balance and pipeline were decribed. The experimental results show that the clock frequency of AES algorithm is up to 127.06 MHz and the throughput eventually achieves 16.26 Gb/s on Xilinx xc7z020clg484 platform, compared with the benchmark AES design, performance increases by three orders of magnitude.

Key words: symmetric key encryption algorithm, Advanced Encryption Standard (AES), High-Level Synthesis (HLS), Field-Programmable Gate Array (FPGA)

中图分类号:

TP309.7

张望, 贾佳, 孟渊, 白旭. 基于高层次综合的AES算法研究与设计[J]. 计算机应用, 2017, 37(5): 1341-1346.

ZHANG Wang, JIA Jia, MENG Yuan, BAI Xu. Research and design of AES algorithm based on high-level synthesis[J]. Journal of Computer Applications, 2017, 37(5): 1341-1346.

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基于高层次综合的AES算法研究与设计

Research and design of AES algorithm based on high-level synthesis

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