计算机应用 ›› 2013, Vol. 33 ›› Issue (02): 450-459.DOI: 10.3724/SP.J.1087.2013.00450

• 信息安全 • 上一篇    下一篇

可重构的串行高级加密标准加解密电路设计

谢惠敏1,郭东辉1,2   

  1. 1. 厦门大学 电子工程系,福建 厦门 361005
    2. 福建省集成电路设计工程技术研究中心,福建 厦门 361005
  • 收稿日期:2012-08-15 修回日期:2012-09-10 出版日期:2013-02-01 发布日期:2013-02-25
  • 通讯作者: 郭东辉
  • 作者简介:谢惠敏(1988-),女,福建厦门人,硕士研究生,主要研究方向:集成电路设计、密码学;
    郭东辉(1967-),男,福建莆田人,教授,博士研究生,主要研究方向:人工智能、网络通信、集成电路设计。

Reconfigurable serial AES encryption and decryption circuit design

XIE Huimin1,GUO Donghui1,2   

  1. 1. Department of Electronic Engineering, Xiamen University, Xiamen Fujian 361005, China
    2. Fujian IC R&D Engineering Center, Xiamen Fujian 361005, China
  • Received:2012-08-15 Revised:2012-09-10 Online:2013-02-01 Published:2013-02-25
  • Contact: GUO Donghui

摘要: 为了进一步提高高级加密标准(AES)算法在现场可编程门阵列(FPGA)上的硬件资源使用效率,提出一种可支持密钥长度128/192/256位串行AES加解密电路的实现方案。该设计采用复合域变换实现字节乘法求逆,同时实现列混合与逆列混合的资源共享以及三种AES算法密钥扩展共享。该电路在Xilinx Virtex-Ⅴ系列的FPGA上实现,硬件资源消耗为1871slice、4RAM。结果表明,在最高工作频率173.904MHz时,密钥长度128/192/256位AES加解密吞吐率分别可达2119/1780/1534Mb·s^(-1)。该设计吞吐率/硬件资源比值较高,且适用支持千兆以太网。

关键词: 高级加密标准, 现场可编程门阵列, 密钥扩展, 加密, 解密

Abstract: To improve the efficiency of hardware resources of the Advanced Encryption Standard (AES) algorithm on the Field Programmable Gate Array (FPGA), an implementation method of serial AES circuit that could perform both encryption and decryption with 128/192/256bit key options was proposed. The design computed byte multiplication inverse in composite field transform, integrated MixColumn and InvMixColumn circuits, and fused three kinds of key expansion algorithms at the same time. The design was implemented in Xilinx FPGA Virtex-Ⅴ and the consumption of hardware resources was 1871slices, 4 block RAM. The results show that the throughput can be up to 2119/1780/1534Mb·s^(-1) for 128/192/256bit key length while the maximum frequency is 173.904MHz. The design achieves high throughput/hardware resource ratio and can be applied to the Gigabit Ethernet.

Key words: Advanced Encryption Standard (AES), Field Programmable Gate Array (FPGA), key-expansion, encryption, decryption

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