Reconfigurable serial AES encryption and decryption circuit design
XIE Huimin1,GUO Donghui1,2
1. Department of Electronic Engineering, Xiamen University, Xiamen Fujian 361005, China 2. Fujian IC R&D Engineering Center, Xiamen Fujian 361005, China
Abstract：To improve the efficiency of hardware resources of the Advanced Encryption Standard (AES) algorithm on the Field Programmable Gate Array (FPGA), an implementation method of serial AES circuit that could perform both encryption and decryption with 128/192/256bit key options was proposed. The design computed byte multiplication inverse in composite field transform, integrated MixColumn and InvMixColumn circuits, and fused three kinds of key expansion algorithms at the same time. The design was implemented in Xilinx FPGA Virtex-Ⅴ and the consumption of hardware resources was 1871slices, 4 block RAM. The results show that the throughput can be up to 2119/1780/1534Mb·s^(-1) for 128/192/256bit key length while the maximum frequency is 173.904MHz. The design achieves high throughput/hardware resource ratio and can be applied to the Gigabit Ethernet.
2013, Vol. 33 
