For the difficulties of achieving accurate clock synchronization in hanwave-in-the-loop network simulation testing using Precise Time Protocol (PTP), the performance of the simulation system of PTP in the face of slave clock frequency drift was studied. The system model and clock model of PTP under hanwave-in-the-loop network environment were established, the time delay estimation error for the master clock estimated by Slaven in unidirectional transmission line was analytically derived. It turned out that each drifting slave led to an additive error of identical structure, these error terms got added both in the drifting slave and its successor, and were then percolated down the line together with the previous accumulated error. Based on this, various network simulation scenarios were designed for verification, analysis and testing. The simulation results show that if only one slave clock drifts, the error at the end of the line is slight; but when all the slave clocks drift, synchronization error is more than 10 times larger, and the same relationship holds for the master versus all slaves drifting, which makes a serious impact on the system synchronization accuracy. The research provides an important reference for the clock deployment strategy in hanwave-in-the-loop network simulation.
孙磊刚, 张明清, 孔红山, 刘小虎. 半实物网络测试系统从时钟频率漂移影响分析[J]. 计算机应用, 2015, 35(3): 624-628.
SUN Leigang, ZHANG Mingqing, KONG Hongshan, LIU Xiaohu. Influence of slave clock frequency drift on hanwave-in-the-loop network testing system. Journal of Computer Applications, 2015, 35(3): 624-628.
[1] MATAR M, KARIMI H, ETEMADI A, et al. A high performance real-time simulator for controllers hardware-in-the-loop testing[J]. Energies, 2012,5(6):1713-1733. [2] SHAN J, MENG X, DING Y, et al. Hardware-in-the-loop simulation[M]. 2nd ed. Beijing: National Defense Industry Press, 2013:7-10.(单家元,孟秀云,丁艳,等.半实物仿真[M].2版.北京:国防工业出版社,2013:7-10.) [3] YOO I D, GOLE A M. Compensating for interface equipment limitations to improve simulation accuracy of real-time power hardware in loop simulation[J]. IEEE Transactions on Power Delivery, 2012,27(3):1284-1291. [4] YANG J, LI Y. Hardware-in-the-loop simulation of communication networks[J]. Journal of Beijing Institute of Technology, 2012,21(3):376-381. [5] MAHMOOD A, EXEL R, SAUTER T. Delay and jitter characterization for software-based clock synchronization over WLAN using PTP[J]. IEEE Transactions on Industrial Informatics, 2014,10(2):1198-1206. [6] FERRARI P, FLAMMINI A, RINALDI S, et al. Experimental characterization of uncertainty sources in a software-only synchronization system[J]. IEEE Transactions on Instrumentation and Measurement, 2012,61(5):1512-1521. [7] SCHEITERER R L, NA C, OBRADOVIC D, et al. Synchronization performance of the precision time protocol in industrial automation networks[J]. IEEE Transactions on Instrumentation and Measurement, 2009,58(6):1849-1857. [8] GIORGI G, NARDUZZI C. Performance analysis of Kalman-filter-based clock synchronization in IEEE 1588 networks[J]. IEEE Transactions on Instrumentation and Measurement, 2011,60(8):2902-2909. [9] ZHUANG X, WANG H. IEEE 1588 clock synchronization algorithm based on Kalman filter[J]. Journal of Electronic Measurement and Instrument, 2012,26(9):747-751.(庄晓燕,王厚军.基于卡尔曼滤波器的 IEEE 1588时钟同步算法[J].电子测量与仪器学报,2012,26(9):747-751.) [10] CIUFFOLETTI A. Preventing the collision of requests from slave clocks in the Precision Time Protocol (PTP)[J].IEEE Transactions on Instrumentation and Measurement, 2011,60(6):2096-2103. [11] LIU Y, YANG C. OMNeT++ based modeling and simulation of the IEEE 1588 PTP clock[C]//Proceedings of the 2011 International Conference on Electrical and Control Engineering. Piscataway: IEEE,2011:4602-4605. [12] WALKER J, CANTONI A. Experimental evaluation of the jitter generated in timing transfer[J]. IEEE Transactions on Communications, 2010,58(12):3605-3612. [13] WEI F, SUN W. Precise time stamping method for IEEE1588 clock synchronization message[J]. Journal of Electronic Measurement and Instrument, 2009,30(1):162-169.(魏丰,孙文杰.协议时钟同步报文的精确时间标记方法研究[J].仪器仪表学报,2009,30(1):162-169.) [14] FERRARI P, FLAMMINI A, RINALDI S, et al. On the seamless interconnection of IEEE1588-based devices using a PROFINET IO infrastructure[J]. IEEE Transactions on Industrial Informatics, 2010,6(3):381-392. [15] EXEL R. Mitigation of asymmetric link delays in IEEE 1588 clock synchronization systems[J]. IEEE Communications Letters, 2014,18(3):507-510.