[1] 周端,彭景,张剑贤,等.低功耗片上网络路由器设计[J].计算机应用,2011,31(10):2621-2624.(ZHOU D, PENG J, ZHANG J X, et al. Low-power NoC router design[J]. Journal of Computer Applications, 2011, 31(10):2621-2624.) [2] SEITANIDIS I, PSARRAS A, CHRYSANTHOU K, et al. ElastiStore:flexible elastic buffering for virtual-channel-based networks on chip[J]. IEEE Transactions on Very Large Scale Integration Systems, 2015, 23(12):3015-3028. [3] 郑小富,顾华玺,杨银堂,等.基于提前分配路径的低时延片上路由器结构[J].电子与信息学报,2013,35(2):341-348.(ZHENG X F, GU H X, YANG Y T, et al. Pre-allocated path based low latency router architecture for network-on-chip[J]. Journal of Electronics & Information Technology, 2013, 35(2):341-348.) [4] OVEIS-GHARAN M, KHAN G N. Efficient dynamic virtual channel organization and architecture for NoC systems[J]. IEEE Transactions on Very Large Scale Integration Systems, 2016, 24(2):465-478. [5] LI C, YANG M, AMPADU P. An energy-efficient NoC router with adaptive fault-tolerance using channel slicing and on-demand TMR[J]. IEEE Transactions on Emerging Topics in Computing, 2016,PP(99):1-1. [6] WANG L, MA S, WANG Z Y. A high performance reliable NoC router[EB/OL].[2016-10-19]. http://www.aspdac.com/aspdac2016/technical_program/pdf/8A-1.pdf. [7] LAI M, GAO L, SHI W, et al. Escaping from blocking:a dynamic virtual channel for pipelined routers[C]//CISIS 2008:Proceedings of the 2008 International Conference on Complex, Intelligent and Software Intensive Systems. Piscataway, NJ:IEEE, 2008:795-800. [8] EVRIPIDOU M, NICOPOULOS C, SOTERIOU V, et al. Virtualizing virtual channels for increased network-on-chip robustness and upgradeability[C]//ISVLSI'12:Proceedings of the 2012 IEEE Computer Society Annual Symposium on VLSI. Washington, DC:IEEE Computer Society, 2012:21-26. [9] NICOPOULOS C A, PARK D, KIM J, et al. ViChaR:a dynamic virtual channel regulator for network-on-chip routers[C]//Proceedings of the 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture. Piscataway, NJ:IEEE, 2006:333-346. [10] XU Y, ZHAO B, ZHANG Y T, et al. Simple virtual channel allocation for high-throughput and high-frequency on-chip routers[C]//HPCA 16:Proceedings of the 16th International Symposium on High-Performance Computer Architecture. Piscataway, NJ:IEEE, 2010:1-11. [11] 姚磊,蔡觉平,李赞,等.基于内建自测技术的Mesh结构NoC无虚通道容错路由算法[J].电子学报,2012,40(5):983-989.(YAO L, CAI J P, LI Z, et al. A fault-tolerant routing algorithm based on BIST for 2D-mesh network-on-chip without using virtual channels[J]. Acta Electronica Sinica, 2012, 40(5):983-989.) [12] LIU J X, HARKIN J, LI Y H, et al. Fault-tolerant networks-on-chip routing with coarse and fine-grained look-ahead[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016, 35(2):260-273. [13] DEORIO A, FICK D, BERTACCO V, et al. A reliable routing architecture and algorithm for NoCs[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012, 31(5):726-739. [14] POLURI P, LOURI A. Shield:a reliable network-on-chip router architecture for chip multiprocessors[J]. IEEE Transactions on Parallel and Distributed Systems, 2016, 27(10):3058-3070 [15] GHOSHAL B, MANNA K, CHATTOPADHYAY S, et al. In-field test for permanent faults in FIFO buffers of NoC routers[J]. IEEE Transactions on Very Large Scale Integration Systems, 2016, 24(1):393-397. [16] VAN DE GOOR A, SCHANSTRA I, ZORIAN Y. BIST for ring-address SRAM-type FIFOs[C]//Proceedings of the 1994 IEEE International Workshop on Memory Technology, Design, and Testing. Piscataway, NJ:IEEE, 1994:112-118. [17] VALINATAJ M, SHAHIRI M. A low-cost, fault-tolerant and high-performance router architecture for on-chip networks[J]. Microprocessors & Microsystems, 2016, 45(PA):151-163. [18] 欧阳一鸣,陈义军,梁华国,等.一种故障通道隔离的低开销容错路由器设计[J].电子学报,2014,42(11):2142-2149.(OUYANG Y M, CHEN Y J, LIANG H G, et al. Design of a low-overhead fault channel isolated fault-tolerant router[J]. Acta Electronica Sinica, 2014, 42(11):2142-2149.) [19] 王坚,李玉柏,蒋勇男.片上网络通信性能分析建模与缓存分配优化算法[J].电子与信息学报,2009,31(5):1059-1062.(WANG J, LI Y B, JIANG Y N. Communication performance analytical model and buffer allocation optimizing algorithm for network-on-chip[J]. Journal of Electronics & Information Technology, 2009, 31(5):1059-1062.) [20] LANGAR M, BOURGUIBA R, MOUINE J. Virtual channel router architecture for network on chip with adaptive inter-port buffers sharing[C]//Proceedings of the 2016 13th International Multi-Conference on Systems, Signals & Devices. Piscataway, NJ:IEEE, 2016:691-694. |