Journal of Computer Applications ›› 2015, Vol. 35 ›› Issue (5): 1421-1425.DOI: 10.11772/j.issn.1001-9081.2015.05.1421

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Key techniques for fast instruction set simulator

FU Lin1, HU Jin1, LIANG Liping2   

  1. 1. College of Physics and Microelectronics, Hunan University, Changsha Hunan 410082, China;
    2. Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
  • Received:2014-12-17 Revised:2015-02-24 Online:2015-05-10 Published:2015-05-14

指令集仿真器的关键技术

付琳1, 胡锦1, 梁利平2   

  1. 1. 湖南大学 物理与微电子科学学院, 长沙 410082;
    2. 中国科学院 微电子研究所, 北京 100029
  • 通讯作者: 付琳
  • 作者简介:付琳(1990-),女,湖南邵阳人,硕士研究生,主要研究方向:多核DSP验证技术; 胡锦(1963-),男,湖南长沙人,教授,主要研究方向:电子系统与专用集成电路; 梁利平(1969-),男,湖北汉川人,研究员,博士,主要研究方向:高性能数字信号处理器/微处理器、高速混合信号集成电路设计.
  • 基金资助:

    湖南省科技计划项目(2014GK3002, 2014GK3148).

Abstract:

In order to adapt to the the requirement of the Instruction Set Simulator (ISS) simulation speed in embedded system development, an improved ISS technology was put forward.The technology introduced instruction preprocessing, dynamic decode cache structure, multi-thread C function generation and dynamic scheduling technique based on the existing static multi-core simulator to achieve the optimization of the simulator performance. This technique has been applied successfully in forming OPT-ISS, which is based on IME-Diamond multi-core DSP processor. The experimental results show that this technique improves the simulation speed indeed.

Key words: multi-core, Instruction Set Simulator (ISS), multi-thread, decoding cache, C function generation

摘要:

为适应嵌入式系统开发中对指令集仿真器仿真速度的要求,提出一种改进的指令集仿真技术.该技术在现有的静态多核仿真器基础上引入指令预处理、动态译码缓存、多线程C函数生成和动态调度运行等技术,以实现对仿真器性能的优化.该技术已成功应用于中国科学院微电子所自主研发的IME-Diamond DSP处理器的多核指令集仿真器OPT-ISS中.实际应用程序测试结果表明,该技术在仿真速度提升方面有明显效果.

关键词: 多核, 指令集仿真器, 多线程, 译码缓存, C函数生成

CLC Number: