Reconfigurable test scheme for 3D stacked integrated circuits based on 3D linear feedback shift register

doi:10.11772/j.issn.1001-9081.2022020186

Journal of Computer Applications ›› 2023, Vol. 43 ›› Issue (3): 949-955.DOI: 10.11772/j.issn.1001-9081.2022020186

• Frontier and comprehensive applications • Previous Articles

Reconfigurable test scheme for 3D stacked integrated circuits based on 3D linear feedback shift register

Tian CHEN¹^,²(), Jianyong LU¹^,², Jun LIU¹^,², Huaguo LIANG³, Yingchun LU³

^1.School of Computer Science and Information Engineering，Hefei University of Technology，Hefei Anhui 230601，China
^2.Anhui Province Key Laboratory of Affective Computing and Advanced Intelligent Machine （Hefei University of Technology），Hefei Anhui 230601，China
^3.School of Microelectronics，Hefei University of Technology，Hefei Anhui 230601，China

Received:2022-02-21 Revised:2022-04-24 Accepted:2022-04-25 Online:2022-08-16 Published:2023-03-10
Contact: Tian CHEN
About author:LU Jianyong， born in 1995， M. S. candidate. His research interests include low-power test for very large-scale integrated circuit/system-on-chip， design for testability.
LIU Jun， born in 1978， Ph. D.， associate professor. His research interests include machine learning acceleration， computer architecture.
LIANG Huaguo， born in 1959， Ph. D.， professor. His research interests include embedded system synthesis and testing， digital system design automation.
LU Yingchun， born in 1979， Ph. D.， lecturer. His research interests include hardware security， integrated circuit design.
Supported by:
National Natural Science Foundation of China(62174048)

基于三维线性反馈移位寄存器的三维堆叠集成电路可重构测试方案

陈田¹^,²(), 鲁建勇¹^,², 刘军¹^,², 梁华国³, 鲁迎春³

^1.合肥工业大学计算机与信息学院, 合肥 230601
^2.情感计算与先进智能机器安徽省重点实验室(合肥工业大学), 合肥 230601
^3.合肥工业大学微电子学院, 合肥 230601

通讯作者: 陈田
作者简介:陈田（1974—），女，安徽合肥人，副教授，博士，CCF高级会员，主要研究方向：超大规模集成电路/系统芯片低功耗测试、可测试性设计、可穿戴计算
鲁建勇（1995—），男，安徽安庆人，硕士研究生，主要研究方向：超大规模集成电路/系统芯片低功耗测试、可测试性设计
刘军（1978—），男，江苏新沂人，副教授，博士，CCF会员，主要研究方向：机器学习加速、计算机体系结构
梁华国（1959—），男，安徽合肥人，教授，博士，CCF高级会员，主要研究方向：嵌入式系统综合与测试、数字系统设计自动化
鲁迎春（1979—），男，安徽桐城人，讲师，博士，主要研究方向：硬件安全、集成电路设计。
基金资助:
国家自然科学基金资助项目(62174048)

Abstract

Abstract:

Due to complex structure of Three-Dimensional Stacked Integrated Circuit （3D SIC）， it is more difficult to design an efficient test structure for it to reduce test cost than for Two-Dimensional Integrated Circuit （2D IC）. For decreasing cost of 3D SIC testing， a Three-Dimensional Linear Feedback Shift Register （3D-LFSR） test structure was proposed based on Linear Feedback Shift Register （LFSR）， which can effectively adapt to different test phases of 3D SIC. The structure was able to perform tests independently in the pre-stacking tests. After the stacking， the pre-stacking test structure was reused and reconfigured into a test structure suitable for the current circuit to be tested， and the reconfigured test structure was able to further reduce test cost. Based on this structure， the corresponding test data processing method and test flow were designed， and the mixed test mode was adopted to reduce the test time. Experimental results show that compared with the dual-LFSR structure， 3D-LFSR structure has the average power consumption reduced by 40.19%， the average area overhead decreased by 21.31%， and the test data compression rate increased by 5.22 percentage points. And， using the hybrid test mode reduces the average test time by 20.49% compared to using the serial test mode.

Key words: three-Dimensional Stacked Integrated Circuits (3D SIC), Linear Feedback Shift Register (LFSR), Design For Testability (DFT), reconfigurable test, test cost

摘要：

三维堆叠集成电路（3D SIC）结构复杂，相较于二维集成电路（2D IC），设计有效的测试结构以降低测试成本更加困难。为降低3D SIC的测试成本，提出一种基于线性反馈移位寄存器（LFSR）的能够有效适应3D SIC不同测试阶段的三维LFSR（3D-LFSR）测试结构。3D-LFSR结构能够在堆叠前独立进行测试；在堆叠后，复用堆叠前的测试结构，并重构为一个适合当前待测电路的测试结构，且重构后的测试结构能进一步降低测试成本。基于3D-LFSR结构，设计了测试数据处理方法和测试流程，并采用混合测试模式以降低测试时间。实验结果表明，相较于双LFSR结构，3D-LFSR结构的平均功耗降低了40.19%，平均面积开销降低了21.31%，测试数据压缩率提升了5.22个百分点；相较于串行测试模式，采用混合测试模式的平均测试时间减少了20.49%。

关键词: 三维堆叠集成电路, 线性反馈移位寄存器, 可测试性设计, 可重构测试, 测试成本

CLC Number:

TN47

Tian CHEN, Jianyong LU, Jun LIU, Huaguo LIANG, Yingchun LU. Reconfigurable test scheme for 3D stacked integrated circuits based on 3D linear feedback shift register[J]. Journal of Computer Applications, 2023, 43(3): 949-955.

陈田, 鲁建勇, 刘军, 梁华国, 鲁迎春. 基于三维线性反馈移位寄存器的三维堆叠集成电路可重构测试方案[J]. 《计算机应用》唯一官方网站, 2023, 43(3): 949-955.

Figures/Tables 14

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电路名称	电路组成	输入数	输出数	触发器数	反相器数	门数
3D-1	s1196s1238	28	28	36	221	816
3D-2	s420s5378	53	50	195	1 853	1 144
3D-3	s13207	62	152	638	5 378	2 573

电路名称	电路组成	输入数	输出数	触发器数	反相器数	门数
3D-1	s1196s1238	28	28	36	221	816
3D-2	s420s5378	53	50	195	1 853	1 144
3D-3	s13207	62	152	638	5 378	2 573

电路名称	测试数据位数	测试数据存储量/bit			测试数据压缩率/%
电路名称	测试数据位数	Parallel-LFSR	双LFSR	3D-LFSR	Parallel-LFSR	双LFSR	3D-LFSR
平均	140 569	9 487	18 263	10 923	93.25	87.01	92.23
3D-1	768	384	624	435	50.00	18.75	43.36
3D-2	12 840	1 260	2 280	2 010	90.19	82.24	84.36
3D-3	408 100	26 818	51 887	30 324	93.43	87.29	92.57

电路名称	测试数据位数	测试数据存储量/bit			测试数据压缩率/%
电路名称	测试数据位数	Parallel-LFSR	双LFSR	3D-LFSR	Parallel-LFSR	双LFSR	3D-LFSR
平均	140 569	9 487	18 263	10 923	93.25	87.01	92.23
3D-1	768	384	624	435	50.00	18.75	43.36
3D-2	12 840	1 260	2 280	2 010	90.19	82.24	84.36
3D-3	408 100	26 818	51 887	30 324	93.43	87.29	92.57

电路名称	测试数据存储量/bit		WTM
电路名称	填充	未填充	未填充	填充
平均	10 923	9 797	15 641 270	10 165 911
3D-1	435	406	3 812	2 590
3D-2	2 010	1 620	424 601	193 621
3D-3	30 324	27 366	46 495 393	30 301 523

Reconfigurable test scheme for 3D stacked integrated circuits based on 3D linear feedback shift register

基于三维线性反馈移位寄存器的三维堆叠集成电路可重构测试方案

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Figures/Tables 14

References 19

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电路名称	面积开销/μm²		平均功耗
电路名称	重构后	未重构	重构	未重构
平均	336.99	378.19	17 708	39 358
3D-1	162.30	151.26	98	198
3D-2	347.31	375.92	3 012	11 894
3D-3	501.36	607.38	50 016	105 982

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电路名称	WTM			平均功耗			峰值功耗
电路名称	Parallel-LFSR	双LFSR	3D-LFSR	Parallel-LFSR	双LFSR	3D-LFSR	Parallel-LFSR	双LFSR	3D-LFSR
平均	21 135 818	15 665 353	10 165 911	39 490	29 317	17 708	48 087	42 367	42 814
3D-1	5 080	4 411	2 590	212	184	98	311	257	302
3D-2	635 791	479 213	193 621	10 597	7 987	3 012	12 428	10 738	8 004
3D-3	62 766 582	46 512 437	30 301 523	107 661	79 781	50 016	131 522	116 107	120 136

电路名称	WTM			平均功耗			峰值功耗
电路名称	Parallel-LFSR	双LFSR	3D-LFSR	Parallel-LFSR	双LFSR	3D-LFSR	Parallel-LFSR	双LFSR	3D-LFSR
平均	21 135 818	15 665 353	10 165 911	39 490	29 317	17 708	48 087	42 367	42 814
3D-1	5 080	4 411	2 590	212	184	98	311	257	302
3D-2	635 791	479 213	193 621	10 597	7 987	3 012	12 428	10 738	8 004
3D-3	62 766 582	46 512 437	30 301 523	107 661	79 781	50 016	131 522	116 107	120 136

电路名称	面积开销/μm²			测试时间开销
电路名称	Parallel-LFSR	双LFSR	3D-LFSR	串行处理	混合处理
平均	344.11	428.26	336.99	281 224	223 596
3D-1	127.68	231.42	162.30	1 792	1 214
3D-2	267.58	319.20	347.31	25 680	19 364
3D-3	637.08	734.16	501.36	816 200	650 210

电路名称	面积开销/μm²			测试时间开销
电路名称	Parallel-LFSR	双LFSR	3D-LFSR	串行处理	混合处理
平均	344.11	428.26	336.99	281 224	223 596
3D-1	127.68	231.42	162.30	1 792	1 214
3D-2	267.58	319.20	347.31	25 680	19 364
3D-3	637.08	734.16	501.36	816 200	650 210