[1] |
WANG Zhoukai, ZHANG Jiong, MA Weigang, WANG Huaijun.
Parallel decompression algorithm for high-speed train monitoring data
[J]. Journal of Computer Applications, 2021, 41(9): 2586-2593.
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[2] |
HUANG Chengcheng, DONG Xiaoxiao, LI Zhao.
Deep pipeline 5×5 convolution method based on two-dimensional Winograd algorithm
[J]. Journal of Computer Applications, 2021, 41(8): 2258-2264.
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[3] |
WANG Xiaofeng, JIANG Penglong, ZHOU Hui, ZHAO Xiongbo.
Design of FPGA accelerator with high parallelism for convolution neural network
[J]. Journal of Computer Applications, 2021, 41(3): 812-819.
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[4] |
XIONG Yong, ZHANG Jia, YU Jiajun, ZHANG Benren, LIANG Xuanzhuo, ZHU Qige.
Intelligent layout optimization algorithm for 3D pipelines of ships
[J]. Journal of Computer Applications, 2020, 40(7): 2164-2170.
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[5] |
ZHU Xiaojie, ZHAO Zihao, DU Yi.
PiFlow: model driven big data pipeline framework
[J]. Journal of Computer Applications, 2020, 40(6): 1638-1647.
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[6] |
CHEN Guihui, YI Xin, LI Zhongbing, QIAN Jiren, CHEN Wu.
Third-party construction target detection in aerial images of pipeline inspection based on improved YOLOv2 and transfer learning
[J]. Journal of Computer Applications, 2020, 40(4): 1062-1068.
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[7] |
YAO Zhicheng, WU Zhihui, YANG Jian, ZHANG Shengkui.
FIR correction filter design and FPGA implementation for array mutual coupling error
[J]. Journal of Computer Applications, 2019, 39(8): 2374-2380.
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[8] |
LI Yingying, GAO Wei, GAO Yuchen, ZHAI Shengwei, LI Pengyuan.
Method for exploiting function level vectorization on simple instruction multiple data extensions
[J]. Journal of Computer Applications, 2017, 37(8): 2200-2208.
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[9] |
YUAN Kaijian, ZHANG Xingming, GAO Yanzhao.
Task partitioning algorithm based on parallelism maximization with multi-objective optimization
[J]. Journal of Computer Applications, 2017, 37(7): 1916-1920.
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[10] |
WANG Shoucheng, XU Jinhui, YAN Yingjian, LI Gongli, JIA Yongwang.
Software pipelining realization method of AES algorithm based on cipher stream processor
[J]. Journal of Computer Applications, 2017, 37(6): 1620-1624.
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[11] |
ZHANG Wang, JIA Jia, MENG Yuan, BAI Xu.
Research and design of AES algorithm based on high-level synthesis
[J]. Journal of Computer Applications, 2017, 37(5): 1341-1346.
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[12] |
TAN Haiqing, CHEN Zhengguo, CHEN Wei, XIAO Nong.
Design of DDR3 protocol parsing logic based on FPGA
[J]. Journal of Computer Applications, 2017, 37(5): 1223-1228.
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[13] |
LI Shenglan, JIANG Hongxu, FU Weijian, CHEN Jiao.
Design of DMA controller for multi-channel transmission system based on PCIe
[J]. Journal of Computer Applications, 2017, 37(3): 691-694.
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[14] |
MAI Taotao, PAN Xiaozhong, WANG Yaqi, SU Yang.
Predefined-class based algorithm for compact regular expression matching
[J]. Journal of Computer Applications, 2017, 37(2): 397-401.
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[15] |
ZHANG Suping, HAN Lin, DING Lili, WANG Pengxiang.
New improved algorithm for superword level parallelism
[J]. Journal of Computer Applications, 2017, 37(2): 450-456.
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