Abstract:

Aiming at the problem that the scale of integrated circuits and the number of on-chip registers are increasing, which makes the verification more difficult, a lightweight register model was proposed. Firstly, a concise underlying structure was designed, and parameterized settings were combined to reduce the memory consumption of the register model at runtime. Then the register verification requirements at different levels such as module level and system level were analyzed, and SystemVerilog language was used to implement various functions required for verification. Finally, the built-in test cases and register model automatic generation tools were developed to reduce the setup time of the verification environment in which the register model was located. The experimental results show that the proposed register model is 21.65% of the Universal Verification Methodology (UVM) register model in term of memory consumption at runtime; in term of function, the proposed register model can be applied to traditional UVM verification environments and non-UVM verification environments, and the functions such as read-write property, reset value and backdoor access path of 25 types of registers are checked. This lightweight register model has good universality and flexibility in engineering practice, meets the needs of register verification, and can effectively improve the efficiency of register verification.

Key words: register model, verification, Python, test case, performance analysis

摘要：

针对集成电路规模扩大、片内寄存器数量激增，导致验证难度加大的问题，提出一种轻量级寄存器模型。首先,设计精简的底层结构，配合参数化设置减少寄存器模型在运行时的内存消耗;然后,分析模块级、系统级等不同层次的寄存器验证需求，使用SystemVerilog语言实现验证所需的各项功能;最后,开发内建测试用例和寄存器模型自动生成工具，缩短寄存器模型所处验证环境的建立时间。实验结果表明，在运行时内存消耗方面，该寄存器模型为通用验证方法学(UVM)寄存器模型的21.65%；在功能方面，可应用于传统的UVM验证环境和非UVM验证环境，对25类寄存器的读写属性、复位值、后门访问路径等功能进行检查。该轻量级寄存器模型在工程实践中拥有良好的通用性和灵活性，满足寄存器验证需求，能有效提高寄存器验证的效率。

关键词: 寄存器模型, 验证, Python, 测试用例, 性能分析