[1]徐宁,洪先龙. 超大规模集成电路物理设计理论与算法[M]. 北京: 清华大学出版社,2009: 241-245.[2]CONG J, LUO G, WEI J, et al. Thermal-aware 3D IC placement via transformation[C]// Proceedings of the the 2007 Conference on Asia South Pacific Design Automation. Japan: Yokohama, 2007: 780-785.[3]GOPLEN B, SAPATNEKAR S. Efficient thermal placement of standard cells in 3D ICs using a force directed approach[C]// Proceedings of the 2003 IEEE/ACM International Conference on Computer-Aided Design. Washington, DC:IEEE Computer Society, 2003: 86-89.[4]GOPLEN B, SAPATNEKAR S. Placement of 3D ICs with thermal and interlayer via considerations[C]// Proceedings of the 44th ACM/IEEE Design Automation Conference. New York: ACM, 2007: 626-631.[5]YAN H, ZHOU Q, HONG X. Efficient thermal aware placement approach integrated with 3D DCT placement algorithm[C]// Proceedings of the 9th International Symposium on Quality Electronic Design. Washington, DC:IEEE Computer Society, 2008: 289-292. [6]HSU M K, CHANG Y W, BALABANOV V. TSV-aware analytical placement for 3D IC designs[C]// Proceedings of the 48th Design Automation Conference. New York: ACM, 2011: 664 - 669.[7]CONG J, LUO G. A multilevel analytical placement for 3D ICs[C]// Proceedings of the 2009 Asia and South Pacific Design Automation Conference. Piscataway: IEEE, 2009: 361-366.[8]NAYLOR W C, DONELLY R, SHA L. Non-linear optimization system and method for wire length and delay optimization for an automatic electric circuit placer: USA, 6301693[P],2001.[9]CHAN T, CONG J, SZE K. Multilevel generalized force-directed method for circuit placement[C]// Proceedings of the 2005 International Symposium on Physical Design. New York: ACM, 2005: 185-192.[10]KAHNG A B, RESA S, WANG Q. Architecture and details of a high quality,large-scale analytical placer[C]// Proceedings of the 2005 IEEE/ACM International Conference on Computer-aided Design. Washington, DC:IEEE Computer Society, 2005: 890-897.[11]CHAN T, CONG J, SHINNERL J, et al. mPL6: Enhanced multilevel mixed-size placement[C]// Proceedings of the 2006 International Symposium on Physical Design. New York: ACM, 2006: 212-214.[12]CHEN T C, JIANG Z W, HSU T C, et al. NTUplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints[J]. IEEE Transactions on CAD, 2008, 27(7):1228-1240.[13]KAHNG A B, WANG Q. Implementation and extensibility of an analytic placer[C]// Proceedings of the 2004 International Symposium on Physical Design. New York: ACM, 2005: 18-25.[14]GAO W C, ZHOU Q, QIAN X, et al. A DyadicCluster method used for non-linear placement[C]// Proceedings of the 13th International Symposium on Quality Electronic Design. Washington, DC:IEEE Computer Society, 2012: 418-423.[15]高文超, 周强, 吕勇强,等. 应用于大规模FPGA的解析式布局算法[J].计算机辅助设计与图形学学报, 2011, 23(11): 1944-1948.[16]IBM-PLACE Benchmarks[EB/OL]. [2013-02-05]. http://er.cs.ucla.edu/benchmarks/ibm-place. |