Journal of Computer Applications ›› 2019, Vol. 39 ›› Issue (8): 2374-2380.DOI: 10.11772/j.issn.1001-9081.2019010131

• Network and communications • Previous Articles     Next Articles

FIR correction filter design and FPGA implementation for array mutual coupling error

YAO Zhicheng, WU Zhihui, YANG Jian, ZHANG Shengkui   

  1. Rocket Force University of Engineering Missile Engineering college, Xi'an Shaanxi 710025, China
  • Received:2019-01-18 Revised:2019-03-11 Online:2019-08-10 Published:2019-04-15
  • Supported by:
    This work is partially supported by the National Natural Science Foundation of China (61501471).


姚志成, 吴智慧, 杨剑, 张盛魁   

  1. 火箭军工程大学 导弹工程学院, 西安 710025
  • 通讯作者: 吴智慧
  • 作者简介:姚志成(1975-),男,湖南邵阳人,教授,博士,主要研究方向:数字信号处理、导航与制导;吴智慧(1995-),男,湖南益阳人,硕士研究生,主要研究方向:数字信号处理;杨剑(1986-),男,四川南充人,副教授,博士,主要研究方向:数字信号处理;张盛魁(1994-),男,山东坟上人,硕士研究生,主要研究方向:数字信号处理。
  • 基金资助:

Abstract: Focusing on the issue that the traditional Finite Impulse Response (FIR) filter slows down operation speed and consumes more resources under high-order conditions, a high-speed and high-order FIR filter design method based on piecewise convolution was proposed. Faster data processing was realized by the method of parallel processing in the frequency domain. Firstly, the design order M of the filter was determined and used as the reference sequence length, and the input digital signal was subjected to M period delay. Secondly, the original sequence and the delay sequence were respectively subjected to Fast Fourier Transform (FFT). Thirdly, the transformed sequences were respectively multiplied by the filter and then subjected to Inverse Fast Fourier Transform. Finally, the merging of the two way data was realized by the method of overlapping reservation. Theoretical analysis and simulation tests show that compared with the traditional distributed method based on Look Up Table (LUT), more than 30% of register resources were saved under the same order by the proposed method. On this basis, the measured data of the experimental platform were used for verification. Experimental results show that compared with the result of uncorrected mutual coupling error, the square root of the corrected amplitude mismatch is less than 1 dB and the root mean square of phase mismatch is less than 0.1 rad. Experimental data fully demonstrate the effectiveness of the method for mutual coupling error correction.

Key words: digital array seeker, mutual coupling error, Finite Impulse Response (FIR) filter, Field-Programmable Gate Array (FPGA), Fast Fourier Transform (FFT)

摘要: 针对传统型FIR滤波器在高阶条件下运算速度变慢与耗费资源增多这一问题,提出一种基于分段卷积的高速高阶FIR滤波器设计方法,通过在频域并行处理的方式实现了数据的快速处理。首先,确定滤波器的设计阶数M并将其作为基准序列长度,对输入的数字信号进行M周期延时;然后,将原序列与延时序列分别作快速傅里叶变换(FFT);其次,将变换后的频域结果分别与滤波器相乘后作快速傅里叶逆变换(IFFT);最后,通过重叠保留的方法实现两路数据的拼接。理论分析与仿真测试表明,与基于查找表(LUT)的传统分布式方法相比,同等阶数下所提方法的寄存器资源节省了30%以上。在此基础上利用实验平台的实测数据进行验证,结果表明,与互耦误差校正前相比,校正后的幅度失配均方根小于1 dB,相位失配均方根小于0.1 rad,实验数据充分展示了该方法对互耦误差校正的有效性。

关键词: 数字阵导引头, 互耦误差, FIR滤波器, 现场编程门阵列, 快速傅立叶变换

CLC Number: