To address the limited accuracy and high complexity of channel estimation in Orthogonal Frequency Division Multiplexing （OFDM） systems， a Deep Neural Network （DNN） based channel estimation algorithm for OFDM systems was proposed. First， the channel estimation and equalization processes used in traditional communication systems were replaced by the proposed algorithm， and the pilot information and data blocks at the receiver were used as input features， enabling rapid learning and estimation of channel characteristics. Second， during the model training phase， OFDM frames containing pilot blocks and data blocks were constructed， and combined with a wireless channel propagation model， a large number of simulated data pairs were generated， thereby ensuring that the training data covered a variety of complex channel environments and noise conditions. Finally， the OFDM system was used to perform a nonlinear mapping of the input-output relationship， transforming this mapping relationship into a task suitable for supervised DNN learning， thereby enabling the trained model to output accurate channel estimation results at the receiver efficiently， as well as recovering the original transmit data reliably and improving overall system performance. At the same time， a key computational module for DNN model training was designed on Field Programmable Gate Array （FPGA） to monitor and optimize the trained model in real time. Experimental results showed that， compared with the Least Squares （LS）， Minimum Mean Square Error （MMSE）， and Discrete Fourier Transform-Least Squares-Wiener （DFT-LS-WIENER） algorithms， at a Signal-to-Noise Ratio （SNR） of 10 dB， the proposed algorithm reduced the Bit Error Rate （BER） by 92.82%， 80.32%， and 72.27%， respectively， and outperformed the above comparative algorithms in Normalized Mean Squared Error （NMSE）. The proposed algorithm has good anti-interference performance and estimation accuracy under complex channel conditions； furthermore， it has moderate resource consumption on an FPGA hardware platform， and controllable operating power consumption， making it suitable for deployment on FPGA.