Test architecture design is the basic and key issue of Integrated Circuit (IC) test, and the design of effective test architecture that meet the needs of IC is of great importance to reduce chip cost, improve product quality and increase product competitiveness. Therefore, a test architecture with several ring scan chains using the same test pin in the round robin manner was proposed, namely RRR Scan. In RRR Scan, the scan flip-flops were designed as multiple ring scan chains, which can work in stealth scan mode, ring shift scan mode and linear scan mode. The ring shift scan mode enables the reuse of test data, thus reducing the size of the test set; the stealth scan mode can shorten the test data shifting path, thus significantly reduing the test shifting power consumption, so that the architecture is a general test architecture with the characteristics of data reuse and low power consumption. In addition, in the architecture, the physically adjacent scan cells can be set into the same ring scan chain with little wiring cost. With stealth scan mode, both the shifting length and the delay of test data can be reduced. Experimental results show that the shifting power consumption can be reduced greatly by RRR Scan, and for S13207 circuit, the shifting power consumption is only 0.42% of that of the linear scan.