Understanding the meaning of mathematical problems is the key for automatic problem solving. However， the accuracy of understanding word problems with complex situations and many parameters is relatively low in previous studies， and the effective optimization solutions need to be further explored and studied. On this basis， a math word problem understanding method integrating commonsense knowledge base and grammatical features was proposed for the classical probability word problems with complex context. Firstly， a classical probability word problem representation model containing seven kinds of key problem-solving parameters was constructed according to text and structure characteristics of the classical probability word problems. Then， based on this model， the task of understanding of word problems was transformed into the problem of solving parameter identification， and a Conditional Random Field （CRF） parameter identification method integrating multi-dimensional grammatical features was presented to solve it. Furthermore， aiming at the problem of implicit parameter identification， a commonsense completion module was added， and an understanding method of math word problems integrating commonsense knowledge base and grammatical features was proposed. Experimental results show that the proposed method has the average F1-score of 93.56% for problem-solving parameter identification， and the accuracy of word problem understanding reached 66.54%， which are better than those of Maximum Entropy Model （MaxEnt）， Bidirectional Long Short-Term Memory-Conditional Random Field （BiLSTM-CRF） and traditional CRF methods. It proves the effectiveness of this method in understanding of classical probability word problems.

For a better trade-off between fault-tolerance mechanism and fault-tolerance overhead in processor reliability research, a fault detection approach for Multi-Processor System-on-Chip (MPSoC) that placed the calculation task of detecting code on redundancy core was proposed in this paper. The approach achieved MPSoC failure detection by placing the calculation and comparison parts of detecting code on redundancy core. The technique required no additional hardware modification, and shortened the design cycle while reducing performance and memory overheads. The verification experiment was implemented on a MPSoC by fault injection and running multiple benchmark programs. Comparing several previous methods of fault detection in terms of capability, area, memory and performance overhead, the experiment results show that the approach is effective and able to achieve a better trade-off between performance and overhead.