Emerging non-volatile, byte-addressable memories like phase-change memory can make data persistent at main memory level instead of storage. Since the read/write latency of Non-Volatile Memory (NVM) is very low, the overhead of software in a NVM system has become the main factor in determining the performance of the entire persistent memory system. Pmfs is a file system specifically designed for NVM. However, it still has an undesirable characteristic:each directory operation (create, open or delete) of Pmfs requires a linear search of the entire directory files, resulting in a cost linearly increased with the number of files in the directory. The performance of Pmfs under various workloads was evaluated and the test showed that the overhead of the directory operations had become the bottleneck of the whole system in some circumstance of particular workloads. To solve this problem, a persistent directory entry index was implemented in Pmfs to speed up directory operations. The experimental results show that under a single directory with 100 000 files, the file creation speed is increased by 12 times, the bandwidth is improved by 27.3%.

Since the new generation of flash-based SSD (Solid-State Drivers) use the DDR3 interface as its interface, SSD must communicate with memory controller correctly. FPGA (Field-Programmable Gate Array) was used to design the DDR3 protocol parsing logic. Firstly, the working principle of DDR3 was introduced to understand the controlling mechanism of memory controller. Next, the architecture of this interface parsing logic was designed, and the key technical points, including clock, writing leveling, delay controlling, interface synchronous controlling were designed by FPGA. Last, the validity and feasibility of the proposed design were proved by the modelsim simulation result and board level validation. In terms of performance, through the test of single data, continuous data and mixed read and write data, the bandwidth utilization of DDR3 interface is up to 77.81%. As the test result shows, the design of DDR3 parsing logic can improve the access performance of storage system.