In view of the problems of high resource consumption and difficulty in balancing computational accuracy and efficiency when implementing symmetric positive definite matrix decomposition algorithms on Field Programmable Gate Array （FPGA）， an LDL^T decomposition acceleration structure based on mixed precision strategy was proposed. In the structure， half-precision numbers were used at the storage level to reduce resource consumption， and single-precision numbers were used at the computational level to ensure computational accuracy and numerical stability. In addition， a parallel pipeline structure of multiple processing units was constructed， and a dual arbitration mechanism was introduced， so as to optimize data scheduling and memory access processes. The acceleration structure was deployed on the xczu4ev-sfvc784 FPGA platform， and experiments were conducted on symmetric positive definite matrices of order 4 to 256 under three parallel configurations of 4PE， 8PE， and 16PE. The results show that the proposed structure has the relative errors of calculation results of the matrix decomposition all within {\mathrm{10}}^{-\mathrm{3}} . Compared with some contrast methods， this structure reduces the occupied LUTs resources by more than 40%， and the occupied DSP resources by 70%. It can be seen that this structure maintains computational accuracy while achieving low hardware overhead and improving throughput， demonstrating excellent scalability and engineering adaptability.