A design and implementation method of Field Programmable Gate Array （FPGA） hardware structure optimization based on Radix 2² Fast Fourier Transformation （R2²FFT） algorithm was proposed to solve the problem that Fast Fourier Transformation （FFT） algorithm requires a lot of resources and time to process large-scale data and thus leading to a low operation speed. Firstly， by using R2²FFT algorithm， a Y-shaped dual parallel array structure combining a sequence conversion function and a pipeline structure was constructed， which reduced the usage number of hardware multipliers and increases throughput of hardware structure， so as to improve operation speed of FFT algorithm on FPGA. Secondly， correlation characteristics of the twiddle factors were adopted in single-stage operation of the R2²FFT pipeline to optimize the on-chip storage resource consumption and reduce storage space by about 50.00%. Finally， scalability of hardware structure was further improved in realizing expansion operations such as \mathrm{2} N points and \mathrm{4} N points based on optimization of N-point R2²FFT algorithm structure. Verilog HDL language and Modelsim were utilized to implement hardware design and simulation， respectively. Then， the proposed method was synthesized and placed-and-routed by using Vivado2018.3 software， and performance analysis was carried out. Experimental results show that compared with four improved FFT hardware implementation methods， the proposed method reduces the operation time by 75.10%， 95.34%， 38.49%， and 49.20%， respectively， which shows significant improvement of the method in operation speed. At the same time， the resource consumption of the proposed method is reasonable and the consumption proportion of the method is low， and the method has characteristics of low operation power consumption and strong scalability.