Journal of Computer Applications ›› 2021, Vol. 41 ›› Issue (7): 2156-2160.DOI: 10.11772/j.issn.1001-9081.2020081665

Special Issue: 前沿与综合应用

• Frontier and comprehensive applications • Previous Articles    

Multiple ring scan chains using the same test pin in round robin manner

ZHANG Ling1, KUANG Jishun2   

  1. 1. School of Software and Internet of Things Engineering, Jiangxi University of Finance and Economics, Nanchang Jiangxi 330013, China;
    2. College of Information Science and Engineering, Hunan University, Changsha Hunan 410082, China
  • Received:2020-10-28 Revised:2021-01-11 Online:2021-07-10 Published:2021-03-29
  • Supported by:
    This work is partially supported by Surface Program of the National Natural Science Foundation of China (61472123), the Key Research Project of Education Department of Hubei Province (D20174501).


张玲1, 邝继顺2   

  1. 1. 江西财经大学 软件与物联网工程学院, 南昌 330013;
    2. 湖南大学 信息科学与工程学院, 长沙 410082
  • 通讯作者: 张玲
  • 作者简介:张玲(1980-),女,安徽淮北人,副教授,博士,CCF会员,主要研究方向:数字集成电路测试、容错计算等;邝继顺(1959-),男,湖南永兴人,教授,博士,主要研究方向:集成电路测试、低成本测试。
  • 基金资助:

Abstract: Test architecture design is the basic and key issue of Integrated Circuit (IC) test, and the design of effective test architecture that meet the needs of IC is of great importance to reduce chip cost, improve product quality and increase product competitiveness. Therefore, a test architecture with several ring scan chains using the same test pin in the round robin manner was proposed, namely RRR Scan. In RRR Scan, the scan flip-flops were designed as multiple ring scan chains, which can work in stealth scan mode, ring shift scan mode and linear scan mode. The ring shift scan mode enables the reuse of test data, thus reducing the size of the test set; the stealth scan mode can shorten the test data shifting path, thus significantly reduing the test shifting power consumption, so that the architecture is a general test architecture with the characteristics of data reuse and low power consumption. In addition, in the architecture, the physically adjacent scan cells can be set into the same ring scan chain with little wiring cost. With stealth scan mode, both the shifting length and the delay of test data can be reduced. Experimental results show that the shifting power consumption can be reduced greatly by RRR Scan, and for S13207 circuit, the shifting power consumption is only 0.42% of that of the linear scan.

Key words: integrated circuit test, design for testing, scan architecture, low-power test, data reuse

摘要: 测试结构设计是集成电路(IC)测试的基础问题也是关键问题,而设计满足当代IC需求的测试结构对降低芯片成本、提高产品质量、增加产品竞争力具有十分重要的意义,为此提出了环形链轮询复用测试端口的测试结构RRR Scan。该结构将扫描触发器设计成多个环形链,环形链可工作于隐身模式、循环移位模式和直链扫描模式。循环移位模式实现了测试数据的重用,可减小测试集规模;隐身模式则可缩短测试数据移位路径,大幅降低测试移位功耗,因此该结构是具有数据重用和低功耗性质的通用测试结构。另外,该结构可将物理上相近的扫描单元设置于同一环形链内,布线代价不大。隐身模式使得测试数据的移位路径长度和时延均有所减小。实验结果表明,RRR Scan结构可大幅降低测试移位功耗,对于S13207电路,其移位功耗仅为扫描直链的0.42%。

关键词: 集成电路测试, 可测试性设计, 扫描结构, 低功耗测试, 数据重用

CLC Number: