Journal of Computer Applications ›› 2020, Vol. 40 ›› Issue (5): 1369-1373.DOI: 10.11772/j.issn.1001-9081.2019091674

• Advanced computing • Previous Articles     Next Articles

Design and implementation of Lite register model

PAN Guoteng, OU Guodong, CHAO Zhanghu, LI Mengjun   

  1. College of Computer Science and Technology, National University of Defense Technology, Changsha Hunan 410073, China
  • Received:2019-10-08 Revised:2019-12-28 Online:2020-05-10 Published:2020-05-15
  • Contact: PAN Guoteng, born in 1977, Ph. D., associate research fellow. His research interests include microprocessor design and verification.
  • About author:PAN Guoteng, born in 1977, Ph. D., associate research fellow. His research interests include microprocessor design and verification.OU Guodong, born in 1977, Ph. D., research assistant. His research interests include microprocessor design and verification.CHAO Zhanghu, born in 1989, M. S., engineer. His research interests include microprocessor design and verification.LI Mengjun, born in 1976, Ph. D., associate professor. His research interests include microprocessor design and verification.
  • Supported by:

    This work is partially supported by the National Science and Technology Major Project of China (2017ZX01028-103-002), the Surface Program of National Natural Science Foundation of China (61672525).


潘国腾, 欧国东, 晁张虎, 李梦君   

  1. 国防科技大学 计算机学院,长沙 410073
  • 通讯作者: 潘国腾(1977—)
  • 作者简介:潘国腾(1977—),男,山东曹县人,副研究员,博士,CCF会员,主要研究方向:微处理器设计与验证; 欧国东(1977—),男,湖南武冈人,助理研究员,博士,主要研究方向:微处理器设计与验证; 晁张虎(1989—),男,河南濮阳人,工程师,硕士,主要研究方向:微处理器设计与验证; 李梦君(1976—),男,湖北云梦人,副教授,博士,主要研究方向:微处理器设计与验证。
  • 基金资助:



Aiming at the problem that the scale of integrated circuits and the number of on-chip registers are increasing, which makes the verification more difficult, a lightweight register model was proposed. Firstly, a concise underlying structure was designed, and parameterized settings were combined to reduce the memory consumption of the register model at runtime. Then the register verification requirements at different levels such as module level and system level were analyzed, and SystemVerilog language was used to implement various functions required for verification. Finally, the built-in test cases and register model automatic generation tools were developed to reduce the setup time of the verification environment in which the register model was located. The experimental results show that the proposed register model is 21.65% of the Universal Verification Methodology (UVM) register model in term of memory consumption at runtime; in term of function, the proposed register model can be applied to traditional UVM verification environments and non-UVM verification environments, and the functions such as read-write property, reset value and backdoor access path of 25 types of registers are checked. This lightweight register model has good universality and flexibility in engineering practice, meets the needs of register verification, and can effectively improve the efficiency of register verification.

Key words: register model, verification, Python, test case, performance analysis



关键词: 寄存器模型, 验证, Python, 测试用例, 性能分析

CLC Number: