Reconfigurable Keccak algorithm and its implementation on FPGA platform

doi:10.3724/SP.J.1087.2012.00864

Journal of Computer Applications ›› 2012, Vol. 32 ›› Issue (03): 864-866.DOI: 10.3724/SP.J.1087.2012.00864

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Reconfigurable Keccak algorithm and its implementation on FPGA platform

WU Wu-fei¹, WANG Yi^1,2,3, LI Ren-fa^1,2,3

1.Embedded Systems and Networking Laboratory, Hunan University, Changsha Hunan 410082, China;
2.Hunan Province Graduate Innovation Base, Hunan University, Changsha Hunan 410082, China;
3.Hunan Province Key Laboratory of Network and Information Security, Hunan University, Changsha Hunan 410082, China

Received:2011-08-11 Revised:2011-11-10 Online:2012-03-01 Published:2012-03-01

Keccak算法|海绵结构|哈希算法|可重构|现场可编程门阵列

吴武飞¹,王奕^1,2,3,李仁发^1,2,3

1.湖南大学嵌入式系统与网络实验室, 长沙 410082;
2.湖南大学湖南省研究生培养创新基地, 长沙 410082;
3.湖南大学网络与信息安全湖南省重点实验室, 长沙 410082

通讯作者: 王奕
作者简介:吴武飞(1986-),男,江西安义人,硕士研究生,CCF会员,主要研究方向:嵌入式系统;王奕(1977-),女,河南洛阳人,讲师,博士,CCF会员,主要研究方向:功耗攻击以及防御、嵌入式安全;李仁发(1957-),男,湖南宜章人,教授,博士,CCF会员,主要研究方向:嵌入式计算、无线传感网络、CPS。
基金资助:
国家自然科学基金资助项目(60873074,60673061);长沙市科技计划项目(K1003028-11)。

Abstract

Abstract: Based on the analysis of Keccak algorithm, concerning the situation that the existing hardware implementations of Keccak algorithm lack of flexibility and could only support one version, this paper proposed a new reconfigurable Keccak hardware implementation, which could support four versions algorithms. The proposed design achieved 214MHz clock frequency using 1607slices when being ported to Xilinx Virtex-5 FPGA platform. The experimental results show that the proposed design has the advantages of high throughput (9131Mbps), good flexibility and supporting four versions.

Key words: Keccak algorithm, sponge structure, Hash algorithm, reconfigurability, Field-Programmable Gate Array (FPGA)

摘要： 在分析研究Keccak算法的基础上,针对现有Keccak算法的硬件实现方案版本单一,应用不灵活的问题,设计了一种高性能可重构的Keccak算法硬件实现方案。实验结果表明:该方案在Xilinx 公司的现场可编程门阵列(FPGA)Virtex-5平台上的时钟频率可达214MHz,占用1607slices;该方案具有吞吐量高(9131Mbps),应用灵活性好,可支持4种不同参数版本的优点。

关键词: KECCAK, 海绵结构, 哈希算法, 可重构, 现场可编程门阵列(FPGA)

CLC Number:

TP332.1

WU Wu-fei WANG Yi LI Ren-fa. Reconfigurable Keccak algorithm and its implementation on FPGA platform[J]. Journal of Computer Applications, 2012, 32(03): 864-866.

吴武飞王奕李仁发. Keccak算法|海绵结构|哈希算法|可重构|现场可编程门阵列[J]. 计算机应用, 2012, 32(03): 864-866.

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Reconfigurable Keccak algorithm and its implementation on FPGA platform

Keccak算法|海绵结构|哈希算法|可重构|现场可编程门阵列

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