Abstract: The Instruction Level Parallelism (ILP) of VLIW DSP processor is acquired through operation partitioning and software pipeline. In the previous research of operation partitioning, people always focus on reducing move operations between clusters, but rarely consider the effect of heterogeneous architecture and some registers that should be placed on reserved cluster. A method based on DataFlow Graph (DFG) for heterogeneous architecture was described to solve this problem. First, the DFG was partitioned into several sub-graphs according to the relations between operations, then the sub-graphs were refined with a heuristic method to meet the requirements of special registers. The experimental results show that this method can make the load of cluster more balanced, and achieve an average of 8% improvement over traditional method.

Key words: Very Long Instruction Word(VLIW), ILP (Instruction Level Parallelism), heterogeneous, operation partitioning, heuristic method

摘要： 超长指令字数字信号处理器(VLIW DSP)的指令级并行性(ILP)主要通过指令分簇和软件流水来实现。在以前的研究中，指令分簇主要只考虑指令级并行性和减少簇间转移指令，对异构体系结构和某些寄存器只能分在指定簇上的情况考虑较少。提出一种基于数据流图(DFG)的异构体系结构上的分簇方法，利用指令的相关性将DFG划分为与簇数目相同个数的子图，再根据特殊寄存器对簇的要求采用启发式算法对子图进行调整，实验结果表明这种分簇方法使得负载更均衡，加速比相对于传统方法可以提高8%左右。

关键词: 超长指令字, 指令级并行性, 异构, 分簇, 启发式算法