[1] RIVEST R. RFC1321, the MD5 message-digest algorithm[S]. Geneva: IETF, 1992. [2] JARVINEN K, TOMMISKA M,SKYTTA J. Hardware implementation analysis of the MD5 Hash algorithm[C]// Proceedings of the 38th Annual Hawaii International Conference on System Sciences. Piscataway: IEEE Press, 2005:298a. [3] HONG Q, ZHOU Q, WANG Y, et al. Research and hardware realization of MD5 algorithm based on Hash function[J]. Computer Engineering, 2013,39(3):137-141.(洪琪,周琴琴,王永亮,等. 基于Hash函数的MD5算法研究和硬件实现[J].计算机工程,2013,39(3):137-141). [4] CHEN S, HUANG W. FPGA Implementation of MD5 algorithm[J]. Information Security and Communications Privacy,2007(6):129-130.(陈松,黄炜. MD5算法的FPGA实现[J].信息安全与通信保密,2007(6):129-130.) [5] LIU K, CHE M, QIN C. A high throughput FPGA implementation of MD5 algorithm[J]. Microprocessors,2008,29(1):188-191.(刘凯,车明,秦存秀. 一种高吞吐量MD5算法的FPGA实现[J]. 微处理机,2008, 29(1):189-190.) [6] MAO X, LI T, SUN Z. NetMagic innovative experimental platform design guide[M]. Changsha: National Defense University Press,2012: 23-52.(毛席龙, 李韬, 孙志刚. NetMagic创新实验平台设计指南[M].长沙:国防科技大学出版社,2012:23-52.) [7] SU Q, CHEN Y, JIA C, et al. Design and implementation of access and control method for NetMagic[C]// Proceedings of the 2011 International Conference on Mechatronic Science, Electric Engineering and Computer. Piscataway: IEEE Press, 2011:346-349. [8] NetMagic. How to develop NetMagic rapidly[EB/OL].[2014-05-10].http://www.netmagic.org/Netmagic_specification&whitepapers/Startup_How%20to%20Develop%20NetMagic%20Rapidly.pdf.(NetMagic.如何开发NetMagic平台[EB/OL].[2014-05-10].http://www.netmagic.org/Netmagic_specification&whitepapers/Startup_How%20to%20Develop%20NetMagic%20Rapidly.pdf.) [9] WANG Y, ZHAO Q, JIANG L, et al. Ultra high throughput implementations for MD5 Hash algorithm on FPGA [C]// Proceedings of the Second International Conference on High Performance Computing and Applications, LNCS 5938. Berlin: Springer-Verlag, 2010: 435-440. [10] LIU T, LOU X. FPGA digital electronic systems design and development examples navigation[M]. Beijing: Posts and Telecom Press,2005:84-126.(刘韬,楼兴华. FPGA数字电子系统设计与开发实例导航[M].北京: 人民邮电出版社,2005:84-126.) [11] ZHOU R, SU L. Quartus II-based digital system Verilog HDL design example explanation[M]. Beijing: Publishing House of Electronics Industry,2010:23-89.(周润景, 苏良碧. 基于Quartus II的数字系统Verilog HDL设计实例详解[M].北京:电子工业出版社,2010:23-89.) |