Abstract: In order to meet the requirements on performance, power, area of float point multiplier in X-DSP, the architecture of X-DSP was studied, and the characteristics of all the instructions related to its float point multiplier were analyzed. A high-performance and low-power float point multiplier, which used Booth 2 encoding algorithm and 4:2 compress tree structure and adopt a 4-stage pipeline structure, was designed and implemented. The floating-point multiplier was also synthesized by using design compiler with 0.13μm CMOS technique of a third-party company. The results show that the frequency is 500MHz, the area of the circuit is 67529.36μm2, and the total circuit power consumption is 22.3424mW.

Key words: 4:2 compression tree, Booth algorithm, IEEE-754, floating-point multiplier, Digital Signal Processor (DSP)

摘要： 为了满足高性能X-DSP浮点乘法器的性能、功耗、面积要求,研究分析了X型DSP总体结构和浮点乘法器指令特点,采用Booth 2编码算法和4∶2压缩树形结构,使用4级流水线结构设计实现了一款高性能低功耗浮点乘法器。使用逻辑综合工具Design Compiler,采用第三方公司0.13μm CMOS工艺库,对所设计的乘法器进行了综合,其结果为工作频率500MHz,面积67529.36μm2,功耗22.3424mW。

关键词: 4∶2压缩树, 布斯算法, IEEE-754, 浮点乘法器, 数字信号处理器