计算机应用 ›› 2017, Vol. 37 ›› Issue (8): 2427-2432.DOI: 10.11772/j.issn.1001-9081.2017.08.2427

• 应用前沿、交叉与综合 • 上一篇    

基于拉格朗日一次插值的船舶故障录波时间同步

黄磊明1, 王黎明1, 陈钟琴2   

  1. 1. 海军工程大学 电气工程学院, 武汉 430000;
    2. 中南民族大学 计算机科学学院, 武汉 430070
  • 收稿日期:2017-03-07 修回日期:2017-05-26 出版日期:2017-08-10 发布日期:2017-08-12
  • 通讯作者: 黄磊明
  • 作者简介:黄磊明(1987-),男,山东烟台人,助理工程师,硕士研究生,主要研究方向:舰船智能化监测与控制、舰船电力系统全面模型及其应用;王黎明(1979-),男,山东烟台人,副教授,博士,主要研究方向:电网自动化调度与管理、嵌入式系统设计与开发;陈钟琴(1996-),女,江西九江人,主要研究方向:计算机编程、人工智能软件。
  • 基金资助:
    国家自然科学基金资助项目(61101206);中国博士后科学基金资助项目(2015M572773)。

Time synchronization of ship fault recording device based on Lagrange once interpolation

HUANG Leiming1, WANG Liming1, CHEN Zhongqin2   

  1. 1. College of Electrical Engineering, Naval University of Engineering, Wuhan Hubei 430000, China;
    2. College of Computer Science, South-Central University for Nationalities, Wuhan Hubei 430070, China
  • Received:2017-03-07 Revised:2017-05-26 Online:2017-08-10 Published:2017-08-12
  • Supported by:
    This work is partially supported by the National Natural Science Foundation of China (61101206) and the Postdoctoral Science Foundation of China (2015M572773).

摘要: 针对外部时钟同步法在船用条件下存在的难以实施、易受干扰、安全性低等问题,提出一种基于插值算法的船舶故障录波时间同步方式。首先,录波主机从合并单元上传的报文中提取出原始采样值和额定延时信息;然后,经时间修正还原真实的采样时刻;最后,利用拉格朗日一次插值运算得到同步时刻的重采样值。Matlab仿真实验表明,幅值误差可以通过适当提高采样频率的方式降低,相位误差对应的等效时延均不超过2 μs;样机实验结果显示,正常条件下有效值误差不超过±0.01%,加入故障信号后,基波和5次谐波的有效值误差分别低于±0.006%和-0.5%,两种情况下的等效时延均不超过-3.5 μs,同步精度达到了IEC61850规定的T4等级。

关键词: 故障录波, 时间同步, 外部时钟, 拉格朗日一次插值, IEC61850

Abstract: Aiming at the problem that the external clock synchronization method is difficult to implement, susceptible to interference and insecure under the marine condition, a time synchronization method of ship fault recording device based on interpolation algorithm was proposed. Firstly, the recording host extracted the original sampling values and the rated delay information from the packets uploaded by the merging units. Secondly, the real sampling time was restored after time correction. Finally, Lagrange once interpolation operation was used to obtain the resampling values at the synchronous time. Simulation on Matlab shows that the amplitude error can be reduced by increasing the sampling frequency appropriately, and the equivalent delay corresponding to the phase error is not more than 2 μs. Prototype test shows that the error of valid values does not exceed ±0.01% under the normal condition, of which the fundamental and 5th harmonic are less than ±0.006% and -0.5% after adding the fault signal. Moreover, both of the equivalent delays are less than -3.5 μs, and the synchronization accuracy is in accordance with the T4 level specified in IEC61850.

Key words: fault recording, time synchronization, external clock, Lagrange once interpolation, IEC61850

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