关键词: DDR3,FPGA,SSD,同步时序设计

Abstract: Abstract: Since the new generation of flash-based SSD use the DDR3 interface as its interface, this SSD must communicate with memory controller correctly ,so we proposed using FPGA to design the DDR3 protocol parsing logic. First ,we introduced the working principle of DDR3 memory so that to understand the controlling mechanism of memory controller; Next, we designed the overall architecture of the interface parsing logic, and using FPGA designed every key technology points, including clock、writing leveling、delay controlling、interface synchronous controlling and buffer controlling. Last, the modelsim simulation result and board level validation proved that the validity and feasibility of this design. In terms of performance, through the test of single data、continuous data and mixed read and write data, we get the bandwidth utilization of DDR3 interface up to 77.81%. This design of DDR3 parsing logic could improve the access performance of storage system.

Key words: DDR3,FPGA,SSD,Synchronous timing design