Research and design of AES algorithm based on high-level synthesis
ZHANG Wang1,2, JIA Jia3, MENG Yuan1,2, BAI Xu1,2
1. Institute of Information Engineering, Chinese Academy of Sciences, Beijing 100093, China; 2. National Engineering Laboratory of Information Security Technologies, Beijing 100093, China; 3. Beijing Special Engineering Design and Research Institute, Beijing 100028, China
Abstract：Due to the increasingly high performance requirements on the Advanced Encryption Standard (AES) algorithm which was widely used, software-based cryptographic algorithms have been increasingly difficult to meet the demands of high-throughput ciper cracking. As a result, more and more encryption algorithms have been accelerated by using Field-Programmable Gate Array (FPGA) platform. Focused on the issue that the development of AES algorithm based on FPGA has high complexity and long development cycle, with High-Level Synthesis (HLS) design methodologies, AES hardware acceleration algorithm was designed by using high-level programming language. Firstly, loop unrolling, etc were used to improve operation parallelism. Secondly, to make full use of on-chip memory and circuit resources, the resource balance optimization technology was used. Finally, the full pipeline structure was added to improve the clock frequency and throughput of the overall design. The detailed analysis and comparison of the benchmark design and different optimized designs with structural expansion, resource balance and pipeline were decribed. The experimental results show that the clock frequency of AES algorithm is up to 127.06 MHz and the throughput eventually achieves 16.26 Gb/s on Xilinx xc7z020clg484 platform, compared with the benchmark AES design, performance increases by three orders of magnitude.
张望, 贾佳, 孟渊, 白旭. 基于高层次综合的AES算法研究与设计[J]. 计算机应用, 2017, 37(5): 1341-1346.
ZHANG Wang, JIA Jia, MENG Yuan, BAI Xu. Research and design of AES algorithm based on high-level synthesis. Journal of Computer Applications, 2017, 37(5): 1341-1346.
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2017, Vol. 37 
