基于Matlab的并行循环冗余校验Verilog代码自动生成方法
薛俊, 段发阶, 蒋佳佳, 李彦超, 袁建富, 王宪全
Parallel cyclic redundancy check Verilog program generating method based on Matlab
XUE Jun, DUAN Fajie, JIANG Jiajia, LI Yanchao, YUAN Jianfu, WANG Xianquan
计算机应用
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2016, (9): 2503
-2507
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DOI: 10.11772/j.issn.1001-9081.2016.09.2503
