Abstract: During underwater signal data transmission process, using Field Programmable Gate Array (FPGA) to calculate Cyclic Redundancy Check (CRC) code with traditional serial calculating method cannot meet the demand of fast computation; however, parallel checking method, which is much faster, has difficulty in practical engineering application because of programming complexity. In order to meet the demand of transmission speed, to eliminate programming difficulty and time waste, a method was proposed to automatically generate parallel CRC code for any length data frames by Matlab. It finished all the mathematical deductions based on matrix method and calculations with the help of Matlab and then generated parallel CRC calculating program which conforms to the Verilog HDL grammar rules. Finally, the CRC calculation program statements generated by Matlab were first simulated in Quartus II 9.0 and then demonstrated by data transmission experiments on a civil towed sonar system. The results prove the validity of the proposed method, its programming and generation can be finished in tens of seconds, and the CRC module can accurately figure out CRC code of every long data frame defined by transmission protocol within requested time.

Key words: Cyclic Redundancy Check (CRC), parallel computing, Matlab, Verilog Hardware Description Language (Verilog HDL), Field Programmable Gate Array (FPGA)

摘要： 在水声信号探测数据的传输过程中，现场可编程门阵列（FPGA）通过传统串行方法对长数据帧进行循环冗余校验（CRC）时无法达到速度要求，而更快速的并行校验方法存在因编程复杂带来的实际工程应用困难问题。为了满足传输对校验速度的需求，降低编程难度和缩短编程时间，设计了一种借助Matlab对任意长度数据帧自动编写并行CRC程序语句的方法。该计算方法基于矩阵法数学原理，借助Matlab完成所有数学推导计算过程，然后直接输出符合Verilog HDL语法规则的并行CRC校验程序语句。通过在Quartus Ⅱ 9.0中仿真，进一步在民用拖曳声呐阵列系统上进行数据传输实验，验证了Matlab自动编程方法的有效性：校验程序的自动编写输出能在几十秒内完成，同时生成的并行CRC校验程序能在满足数据传输速度要求的情况下正确地计算出系统中传输协议定义的长数据帧的校验码。

关键词: 循环冗余校验, 并行计算, Matlab, Verilog硬件描述语言, 现场可编程门阵列