计算机应用 ›› 2017, Vol. 37 ›› Issue (5): 1223-1228.DOI: 10.11772/j.issn.1001-9081.2017.05.1223

• 第22届全国信息存储技术学术会议 • 上一篇    下一篇

基于FPGA的DDR3协议解析逻辑设计

谭海清1,2, 陈正国1,2, 陈微1,2, 肖侬1,2   

  1. 1. 国防科学技术大学 计算机学院, 长沙 410073;
    2. 高性能计算国家重点实验室(国防科学技术大学), 长沙 410073
  • 收稿日期:2016-07-15 修回日期:2016-11-30 出版日期:2017-05-10 发布日期:2017-05-16
  • 通讯作者: 谭海清
  • 作者简介:谭海清(1991-),男,湖南衡阳人,硕士研究生,主要研究方向:内存控制、固态存储;陈正国(1991-),男,浙江温州人,博士研究生,主要研究方向:高性能存储、数据重删;陈微(1982-),女,江苏苏州人,副教授,博士,主要研究方向:高性能微处理器、计算机系统结构;肖侬(1969-),男,江西南昌人,教授,博士,CCF会员,主要研究方向:高性能计算、大规模网络存储。
  • 基金资助:
    国家自然科学基金资助项目(NSFC61433019,NSFC61472432)。

Design of DDR3 protocol parsing logic based on FPGA

TAN Haiqing1,2, CHEN Zhengguo1,2, CHEN Wei1,2, XIAO Nong1,2   

  1. 1. College of Computer, National University of Defense Technology, Changsha Hunan 410073, China;
    2. State Key Laboratory of High Performance Computing(National University of Defense Technology), Changsha Hunan 410073, China
  • Received:2016-07-15 Revised:2016-11-30 Online:2017-05-10 Published:2017-05-16
  • Supported by:
    This work is partially supported by the National Natural Science Foundation of China (NSFC61433019, NSFC61432472).

摘要: 针对采用DDR3接口来设计的新一代闪存固态盘(SSD)需要完成与内存控制器进行通信与交互的特点,提出了基于现场可编程门阵列(FPGA)的DDR3协议解析逻辑方案。首先,介绍了DDR3内存工作原理,理解内存控制器对存储设备的控制机制;然后,设计了接口协议解析逻辑的总体架构,采用FPGA实现并对其中的各个关键技术点,包括时钟、写平衡、延迟控制、接口同步控制等进行详细阐述;最后,通过modelsim仿真并进行板级验证,证明了该设计的正确性和可行性。在性能方面,通过单次读写、连续读写和混合读写三种模式下的数据读写测试,取得了最高77.81%的DDR3接口带宽利用率,在实际的SSD开发过程中能够有效提高系统的访问性能。

关键词: 现场可编程门阵列, 固态盘, 同步时序设计, DDR3接口

Abstract: Since the new generation of flash-based SSD (Solid-State Drivers) use the DDR3 interface as its interface, SSD must communicate with memory controller correctly. FPGA (Field-Programmable Gate Array) was used to design the DDR3 protocol parsing logic. Firstly, the working principle of DDR3 was introduced to understand the controlling mechanism of memory controller. Next, the architecture of this interface parsing logic was designed, and the key technical points, including clock, writing leveling, delay controlling, interface synchronous controlling were designed by FPGA. Last, the validity and feasibility of the proposed design were proved by the modelsim simulation result and board level validation. In terms of performance, through the test of single data, continuous data and mixed read and write data, the bandwidth utilization of DDR3 interface is up to 77.81%. As the test result shows, the design of DDR3 parsing logic can improve the access performance of storage system.

Key words: Field-Programmable Gate Array (FPGA), Solid-State Driver (SSD), synchronous timing design, DDR3 interface

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