Dual priority dynamic scheduling algorithm based on multi-FPGA
DU Shuangzhi1, WANG Yong2*, TAO Xiaoling3
1.College of Electronic Engineering and Automation, Guilin University of Electronic Technology, Guilin Guangxi 541004, China;
2.College of Computer Science and Engineering, Guilin University of Electronic Technology, Guilin Guangxi 541004, China; 3.College of Information and Communication, Guilin University of Electronic Technology, Guilin Guangxi 541004, China
Abstract：When single Field-Programmable Gate Array (FPGA) deals with the huge amounts of data in high-speed network, low efficiency problem occurs. According to dual priority schedule algorithm for multi-processor and high-speed data acquisition and processing model based on multi-FPGA, a dual priority dynamic scheduling algorithm was proposed based on multi-FPGA. For strong real-time periodic tasks set in low priority queue, the Earliest Deadline Critical Laxity (EDCL) scheduling algorithm was given to determine the priority of task according to the degree of relaxation of the tasks. If the task was not finished when the promotion time was up, it would be promoted to high priority queue. For soft real-time periodic tasks, an algorithm was put forward to assign the tasks to middle priority queue and schedule them by delaying the deadline of tasks to dynamic blur threshold. The experimental results show that the proposed algorithms can well schedule strong real-time periodic tasks and guarantee the priority execution of important tasks, and it can also reduce miss rate of soft real-time periodic tasks caused by preemption.
杜双枝 王勇 陶晓玲. 基于多片FPGA的双优先级动态调度算法[J]. 计算机应用, 2013, 33(03): 862-865.
DU Shuangzhi WANG Yong TAO Xiaoling. Dual priority dynamic scheduling algorithm based on multi-FPGA. Journal of Computer Applications, 2013, 33(03): 862-865.
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2013, Vol. 33 
