SoC总线的低功耗分支编码方案

计算机应用 ›› 2014, Vol. 34 ›› Issue (12): 3633-3636.

SoC总线的低功耗分支编码方案

李栋¹,王小力¹,杨斌¹,赵长睿²

1. 西安交通大学电子与信息工程学院, 西安 710049
2. 北京大学软件与微电子学院,北京,100871

收稿日期:2014-06-19 修回日期:2014-08-12 发布日期:2014-12-31 出版日期:2014-12-01
通讯作者: 李栋
作者简介:李栋(1990-）,男,陕西咸阳人,硕士研究生,主要研究方向:片上系统低功耗设计；王小力(1956-）,男,江苏无锡人,教授,主要研究方向:高性能VLSI设计；杨斌(1989-）,男,陕西宝鸡人,硕士研究生,主要研究方向:可测性设计；赵长睿(1989-）,男,黑龙江齐齐哈尔人,硕士研究生,主要研究方向:数字图像处理。
基金资助:
国家自然科学基金资助项目

Low power branch encoding scheme based on SoC bus

LI Dong¹,WANG Xiaoli¹,YANG Bin¹,ZHAO Changrui²

1. School of Electronics and Information Engineering, Xi'an Jiaotong University, Xi'an Shaanxi 710049, China;
2. School of Software and Microelectronics, Peking University, Beijing 100871, China

Received:2014-06-19 Revised:2014-08-12 Online:2014-12-31 Published:2014-12-01
Contact: LI Dong

摘要/Abstract

摘要：

为了降低SoC总线功耗,提出一种总线低功耗分支编码。该编码的基本思想为:对于地址总线,当地址连续时将地址总线死锁,当地址不连续时动态地调整窗口大小对其进行翻转编码；对于数据总线,对不同数据位宽分别设置两个汉明距阈值,当汉明距落在两个阈值之间则查找有效数据通道翻转密集区并对该区取反,两个阈值之外则采用翻转编码。该方法的编解码电路在32位AHB总线系统上实现,实验证明该方法与未编码之前相比将地址总线跳变率降低了51.2%,数据总线跳变率降低了22.4%,系统总功耗降低了28.9%。将T0编码、BI编码等方法在相同系统下实现后与所提方法作比较,证明分支编码方法在降低跳变率和功耗上有明显的优势。

Abstract:

A low power branch encoding method was presented for decreasing the SoC bus power dissipation. This method's basic principle is: for the address bus, when the address bus is sequential, the address bus is frozen, and when the address bus is non-sequential, the window size is adjusted dynamically to apply the Bus-Invert (BI) method on the address bus. For the data bus, two threshold values are figured out for different data size respectively. If the Hamming distance locates between these two threshold values, the valid-data-channel switching dense area is found and inverted, otherwise applies the BI encoding. This method's encoding and decoding circuits are realized in the Advanced High Performance Bus (AHB) system. The experimental result demonstrates that compared with uncoded situation, this method decreases the address/data bus toggle rate by 51.2%/22.4%, and the system power is reduced by 28.9%. Compared with T0,BI and other encoding methods realized in the same system, the branch encoding is more superior in the toggle rate and power dissipation.

中图分类号:

TP331.1

李栋王小力杨斌赵长睿. SoC总线的低功耗分支编码方案[J]. 计算机应用, 2014, 34(12): 3633-3636.

LI Dong WANG Xiaoli YANG Bin ZHAO Changrui. Low power branch encoding scheme based on SoC bus[J]. Journal of Computer Applications, 2014, 34(12): 3633-3636.

参考文献

［1］BENINI L,DEMICHELI G,MACII E, et al. Asymptotic zero-transition activity encoding for address buses in low-power microprocessor-based systems［C］// Proceedings of 7th Great Lakes Symposium on VLSI. Piscataway: IEEE,1997:77-82.
［2］AGHAGHIRI Y,FALLAH F,PEDRAM M. Irredundant address bus encoding for low power［J］. Low Power Electronics and Design,2001,15(8):182-187.
［3］AGHAGHIRI Y, FALLAH F,PEDRAM M. ALBORZ: address level bus power optimization［J］. Quality Electronics Design, 2002,7(11):470-475.
［4］HUI G, PARAMESWARAN S. Shifted gray encoding to reduce instruction memory address bus switching for low-power embedded systems［J］. Journal of Systems Architecture,2010, 56(4/5/6).180-190.
［5］BRAJESH KUMAR K,DEEPIKA A,NAGENDRA G. Bus encoder design for reduced crosstalk, power and area in coupled VLSI interconnects［J］. Microelectronics Journal,2013,44(9): 827-833.
［6］MUSSOLL E,LANG T,CORTADELLA J.Working-zone encoding for reducing the energy in microprocessor address buses［J］. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1998, 6(4): 568-572.
［7］STAN M R, BURLESON W P. Bus-invert coding for low-power I/O［J］.IEEE Transactions on Very Large Scale Integration Systems,1995, 3(1):49-58.
［8］HONG S, NARAYANAN U, CHUNGK S, et al. Bus-invert coding for low-power I/O:a decomposition approach［C］// Proceedings of the 2004 Euromicro Symposium on Digital System Design. Piscataway: IEEE,2004: 190-194.
［9］MEHRNAMI S,MORADINASAB M,YOUSEFI R. Improved weighted code mapping for buses with non uniform data distribution［J］.Design and Test Workshop, 2009, 18(9): 1-4.
［10］ARM. AMBA specifications［EB/OL］.［2014-06-20］.http://www.arm.com.
［11］YIN L,FENG Q,YUAN G.Low power bus encoding technology［J］.Computer Engineering,2008, 34(15):238-240.(尹立群,冯庆,袁国顺.低功耗总线编码技术［J］.计算机工程,2008, 34(15).238-240.)
［12］GE H, XU C,CHEN N, et al. A low power consumption of the embedded system bus oriented optimization method ［J］. Computer Science, 2013, 40(12): 31-36. (葛红美, 徐超, 陈念, 等. 一种面向嵌入式系统总线的低功耗优化方法［J］. 计算机科学, 2013, 40(12): 31-36.)