三维芯片多层与多核并行测试调度优化方法

doi:10.11772/j.issn.1001-9081.2017123002

计算机应用 ›› 2018, Vol. 38 ›› Issue (6): 1795-1800.DOI: 10.11772/j.issn.1001-9081.2017123002

• 应用前沿、交叉与综合 • 上一篇下一篇

三维芯片多层与多核并行测试调度优化方法

陈田^1,2, 汪加伟^1,2, 安鑫^1,2, 任福继^1,2,3

1. 合肥工业大学计算机与信息学院, 合肥 230601;
2. 情感计算与先进智能机器安徽省重点实验室(合肥工业大学), 合肥 230601;
3. 德岛大学工学部, 日本德岛 770-8506)

收稿日期:2017-12-21 修回日期:2018-02-10 出版日期:2018-06-10 发布日期:2018-06-13
通讯作者: 陈田
作者简介:陈田(1974-),女,安徽合肥人,副教授,博士,CCF高级会员,主要研究方向:超大规模集成电路/系统芯片低功耗测试、可测试性设计、可穿戴计算;汪加伟(1992-),男,安徽铜陵人,硕士研究生,主要研究方向:超大规模集成电路/系统芯片低功耗测试、可测试性设计;安鑫(1979-),男,山东潍坊人,副教授,博士,CCF会员,主要研究方向:嵌入式系统、基于可编程逻辑门阵列的动态重构架构;任福继(1959-),男,四川南充人,教授,博士,主要研究方向:情感计算、智能机器人。
基金资助:
国家自然科学基金资助项目（61474035，61204046，61432004，61306049）。

Parallel test scheduling optimization method for three-dimensional chip with multi-core and multi-layer

CHEN Tian^1,2, WANG Jiawei^1,2, AN Xin^1,2, REN Fuji^1,2,3

1. School of Computer Science and Information Engineering, Hefei University of Technology, Hefei Anhui 230601, China;
2. Anhui Provincial Key Laboratory of Affective Computing and Advanced Intelligent Machine(Hefei University of Technology), Hefei Anhui 230601, China;
3. Faculty of Engineering, The University of Tokushima, Tokushima Japan 770-8506, Japan

Received:2017-12-21 Revised:2018-02-10 Online:2018-06-10 Published:2018-06-13
Supported by:
This work is partially supported by the National Natural Science Foundation of China (61474035, 61204046, 61432004, 61306049).

摘要/Abstract

摘要： 针对测试环节在三维（3D）芯片制造过程中成本过高的问题，提出一种基于时分复用（TDM）的协同优化各层之间、层与核之间测试资源的调度方法。首先，在3D芯片各层配置移位寄存器，通过移位寄存器组对输入数据的控制，实现对各层之间以及同一层的各个芯核之间的测试频率的合理划分，使位于不同位置的芯核能够被并行测试；其次，使用贪心算法优化寄存器的分配，减少芯核并行测试的空闲周期；最后，采用离散二进制粒子群优化（DBPSO）算法求出最优3D堆叠的布图，以便充分利用硅通孔（TSV）的传输潜力，提高并行测试效率，减少测试时间。实验结果表明，在功耗约束下，优化后整个测试访问机制（TAM）利用率平均上升16.28%，而3D堆叠的测试时间平均下降13.98%。所提方法减少了测试时间，降低了测试成本。

关键词: 三维测试, 时分复用, 测试调度, 芯核布图优化, 离散二进制粒子群优化算法

Abstract: In order to solve the problem of high cost of chip testing in the process of Three-Dimensional (3D) chip manufacturing, a new scheduling method based on Time Division Multiplexing (TDM) was proposed to optimize the testing resources between layers, layer and core cooperatively. Firstly, the shift registers were arranged on each layer of 3D chip, and the testing frequency was divided properly between the layers and cores of the same layer under the control of shift register group on input data, so that the cores in different locations could be tested in parallel. Secondly, greedy algorithm was used to optimize the allocation of registers for reducing the free test cycles of core parallel test. Finally, Discrete Binary Particle Swarm Optimization (DBPSO) algorithm was used to find out the best 3D stack layout, so that the transmission potential of the Through Silicon Via (TSV) could be adequately used to improve the parallel testing efficiency and reduce the testing time. The experimental results show that, under the power constraints, the utilization rate of the optimized whole Test Access Mechanism (TAM) is increased by an average of 16.28%, and the testing time of the optimized 3D stack is reduced by an average of 13.98%. The proposed method can decrease the time and reduce the cost of testing.

Key words: Three-Dimensional (3D) test, Time Division Multiplexing (TDM), test scheduling, core layout optimization, Discrete Binary Particle Swarm Optimization (DBPSO) algorithm

中图分类号:

TP391.7

陈田, 汪加伟, 安鑫, 任福继. 三维芯片多层与多核并行测试调度优化方法[J]. 计算机应用, 2018, 38(6): 1795-1800.

CHEN Tian, WANG Jiawei, AN Xin, REN Fuji. Parallel test scheduling optimization method for three-dimensional chip with multi-core and multi-layer[J]. Journal of Computer Applications, 2018, 38(6): 1795-1800.

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三维芯片多层与多核并行测试调度优化方法

Parallel test scheduling optimization method for three-dimensional chip with multi-core and multi-layer

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