Abstract: To solve the problem that software implementation cannot meet real-time requirements, a hardware scheme based on Field-Programmable Gate Array (FPGA) was presented. By analyzing the digital watermark extraction system, a watermark-embedding algorithm suitable for FPGA implementation was designed and its structure is applicable to 5/3 wavelet transform. Moreover, a new watermark extraction structure that corresponded to the embedding algorithm was also proposed. The pipeline and highly parallel structure has the features of high computation efficiency, small size, low-power and real-time process. The simulation results demonstrate the system's correctness and the algorithm's abroad applicability.

Key words: digital watermark extraction, Field-Programmable Gate Array (FPGA), 5/3 wavelet transform, pipeline, parallelism

摘要： 针对传统软件实现数字水印系统难以满足实时性的问题,提出了基于现场可编程门阵列(FPGA)的硬件实现方案。通过对数字水印提取系统进行深入研究,设计了易于FPGA实现的数字水印算法和适用于5/3小波变换的算法结构,并进一步设计出与算法相对应的新的水印提取结构。该结构体现了流水线和高度并行性,计算效率高,具有体积小、功耗低、实时性强等特点。经仿真验证证实了所设计系统的正确性,算法结构具有广泛的适用性。

关键词: 数字水印提取, 现场可编程门阵列, 5/3小波变换, 流水线, 并行