[1] |
Yunfei SHEN, Fei SHEN, Fang LI, Jun ZHANG.
Deep neural network model acceleration method based on tensor virtual machine
[J]. Journal of Computer Applications, 2023, 43(9): 2836-2844.
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[2] |
Yingjie MA, Jing XIAO, Geng ZHAO, Ping ZENG, Yatao YANG.
Controllable grid multi-scroll chaotic system family and its hardware circuit implementation
[J]. Journal of Computer Applications, 2023, 43(3): 956-961.
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[3] |
Binwei SONG, Yao WANG.
Low-cost pay-per-use licensing scheme for FPGA intellectual property protection
[J]. Journal of Computer Applications, 2023, 43(10): 3142-3148.
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[4] |
WANG Zhoukai, ZHANG Jiong, MA Weigang, WANG Huaijun.
Parallel decompression algorithm for high-speed train monitoring data
[J]. Journal of Computer Applications, 2021, 41(9): 2586-2593.
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[5] |
HUANG Chengcheng, DONG Xiaoxiao, LI Zhao.
Deep pipeline 5×5 convolution method based on two-dimensional Winograd algorithm
[J]. Journal of Computer Applications, 2021, 41(8): 2258-2264.
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[6] |
WANG Xiaofeng, JIANG Penglong, ZHOU Hui, ZHAO Xiongbo.
Design of FPGA accelerator with high parallelism for convolution neural network
[J]. Journal of Computer Applications, 2021, 41(3): 812-819.
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[7] |
XU Yingxin, SUN Lei, ZHAO Jiancheng, GUO Songhui.
Virtual field programmable gate array placement strategy based on ant colony optimization algorithm
[J]. Journal of Computer Applications, 2020, 40(3): 747-752.
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[8] |
LEI Xiaokang, YIN Zhigang, ZHAO Ruilian.
FPGA-based convolutional neural network fixed-point acceleration
[J]. Journal of Computer Applications, 2020, 40(10): 2811-2816.
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[9] |
YAO Zhicheng, WU Zhihui, YANG Jian, ZHANG Shengkui.
FIR correction filter design and FPGA implementation for array mutual coupling error
[J]. Journal of Computer Applications, 2019, 39(8): 2374-2380.
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[10] |
LI Yingying, GAO Wei, GAO Yuchen, ZHAI Shengwei, LI Pengyuan.
Method for exploiting function level vectorization on simple instruction multiple data extensions
[J]. Journal of Computer Applications, 2017, 37(8): 2200-2208.
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[11] |
YUAN Kaijian, ZHANG Xingming, GAO Yanzhao.
Task partitioning algorithm based on parallelism maximization with multi-objective optimization
[J]. Journal of Computer Applications, 2017, 37(7): 1916-1920.
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[12] |
WANG Shoucheng, XU Jinhui, YAN Yingjian, LI Gongli, JIA Yongwang.
Software pipelining realization method of AES algorithm based on cipher stream processor
[J]. Journal of Computer Applications, 2017, 37(6): 1620-1624.
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[13] |
ZHANG Wang, JIA Jia, MENG Yuan, BAI Xu.
Research and design of AES algorithm based on high-level synthesis
[J]. Journal of Computer Applications, 2017, 37(5): 1341-1346.
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[14] |
TAN Haiqing, CHEN Zhengguo, CHEN Wei, XIAO Nong.
Design of DDR3 protocol parsing logic based on FPGA
[J]. Journal of Computer Applications, 2017, 37(5): 1223-1228.
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[15] |
LI Shenglan, JIANG Hongxu, FU Weijian, CHEN Jiao.
Design of DMA controller for multi-channel transmission system based on PCIe
[J]. Journal of Computer Applications, 2017, 37(3): 691-694.
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