Abstract: Concerning the problems of too much resource consumption and too low processing speed, a new highorder FIR filter targeted Field Programmable Gate Array (FPGA) was proposed. Firstly, polyphase decomposition architecture and pipeline technology were adopted to decompose highorder FIR filter into loworder ones, and then the proposed MA distributed algorithm architecture was used to implement the decomposed filters in the method. A series of serial and parallel FIR filters which order from 8 to 256 were implemented by ISE10.1 targeted Xilinx Xc2vp307ff896 FPGA device. The experimental results show that the proposed method effectively reduces the system resource consumption and improves the timing performance of the system.

Key words: FIR filter, MA distributed algorithm, polyphase decomposition, pipeline technology, Field Programmable Gate Array (FPGA)

摘要： 针对利用现有分布式算法在FPGA上实现高阶FIR滤波器时,存在资源消耗量过大和运行速度慢等问题,提出一种新型高阶FIR滤波器的FPGA实现方法。首先综合采用多相分解结构、流水线等技术对高阶FIR滤波器进行降阶处理,然后采用提出的基于二输入开关和加法器对的分布式算法结构(MA型DA结构)实现降阶后的FIR滤波器。利用ISE10.1在Xilinx Xc2vp307ff896 FPGA开发板上实现了一系列8阶到256阶的串行和并行结构FIR滤波器。实验结果表明，该方法有效地减少了系统的资源消耗,提高了系统的时序性能。

关键词: FIR滤波器, MA型分布式算法, 多相分解, 流水线, 现场可编程门阵列