关键词: 半加器, Verilog, 整数加法器, 现场可编程门阵列

Abstract: To accelerate the adder, a new parallel integer addition algorithm - carry barrel adder algorithm was proposed. The adder applied half-adder, combining parallel and iterative feedback ideas, judging the completion of a summation according to the value of the carry chain produced after each round of iteration, which can maintain the acceleration of calculation on low power consumption. The simulation results show that the proposed design of the barrel integer adder can accelerate prominently in slight augmentation of areas.

Key words: half-adder, Verilog, integer adder, Field-Programmable Gate Array (FPGA)