VLIW处理器循环指令缓冲器设计与实现

doi:10.11772/j.issn.1001-9081.2014.04.1005

计算机应用 ›› 2014, Vol. 34 ›› Issue (4): 1005-1009.DOI: 10.11772/j.issn.1001-9081.2014.04.1005

VLIW处理器循环指令缓冲器设计与实现

李勇,胡慧俐,杨焕荣

国防科学技术大学计算机学院，长沙 410073

收稿日期:2013-10-18 修回日期:2013-11-14 出版日期:2014-04-01 发布日期:2014-04-29
通讯作者: 李勇
作者简介:李勇(1970-),男,安徽利辛人,副研究员,博士,主要研究方向:微处理器体系结构;
胡慧俐(1969-),女,湖南桃江人,副研究员,硕士,主要研究方向:计算机网络;
杨焕荣(1985-),男,湖南永州人,助理研究员,硕士,主要研究方向:微处理器设计。
基金资助:
国家自然科学基金资助项目

Design and implementation of loop instruction buffer in VLIW processor

LI Yong,HU Huili,YANG Huanrong

School of Computer Science, National University of Defense Technology, Changsha Hunan 410073, China

Received:2013-10-18 Revised:2013-11-14 Online:2014-04-01 Published:2014-04-29
Contact: LI Yong

摘要/Abstract

摘要：

数字信号处理软件中循环程序在执行时间上占有很大比例，用指令缓冲器暂存循环代码可以减少程序存储器的访问次数，提高处理器性能。在VLIW处理器指令流水线中增加一个支持循环指令的缓冲器，该缓冲器能够缓存循环程序指令，并以软件流水的形式向功能部件派发循环程序指令。这样循环程序代码只需访存一次而执行多次，大大减少了访存次数。在循环指令运行期间，缓冲器发出信号使程序存储器进入睡眠状态可以降低处理器功耗。典型的应用程序测试表明，使用了循环缓冲后，取指流水线空闲率可达90%以上，处理器整体性能提高10%左右，而循环缓冲的硬件面积开销大约占取指流水线的9%。

Abstract:

Loop program has a significant amount of execution time in digital signal processing software, temporary storage of loop code with instruction buffer can reduce the number of program memory access to improve the performance of processor. A loop instruction buffer was added in the instruction pipeline. It could store and dispatch instructions of loop program in the software pipelining manner. The instructions of loop program needed to be accessed from program memory only once but executed many times, so the number of memory access was reduced. During the loop instructions were dispatched from buffer, the program memory could be signaled to sleep to reduce the power consumption of processor. In the typical application program, the instruction pipeline can be idle above 90%, and the performance of processor is improved about 10%, the overhead of loop buffer is 9% of the instruction pipeline.

中图分类号:

TP301.6

李勇胡慧俐杨焕荣. VLIW处理器循环指令缓冲器设计与实现[J]. 计算机应用, 2014, 34(4): 1005-1009.

LI Yong HU Huili YANG Huanrong. Design and implementation of loop instruction buffer in VLIW processor[J]. Journal of Computer Applications, 2014, 34(4): 1005-1009.

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VLIW处理器循环指令缓冲器设计与实现

Design and implementation of loop instruction buffer in VLIW processor

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