计算机应用 ›› 2014, Vol. 34 ›› Issue (12): 3628-3632.

• 行业与领域应用 • 上一篇    下一篇

面向测试优化的片上网络映射算法

张颖,吴宁,葛芬   

  1. 南京航空航天大学 电子信息工程学院,南京 210016
  • 收稿日期:2014-05-19 修回日期:2014-07-08 出版日期:2014-12-01 发布日期:2014-12-31
  • 通讯作者: 张颖
  • 作者简介:张颖(1977-),女,江苏南京人,讲师,博士研究生,主要研究方向:数字系统设计、集成电路设计与测试;吴宁(1956-),女,安徽淮南人,教授,主要研究方向:数字系统设计、集成电路设计;葛芬(1981-),女,江苏丹阳人,副教授,博士,主要研究方向:片上网络设计、系统级建模。
  • 基金资助:

    国家自然科学基金资助项目;国防基础科研项目;江苏省科技支撑计划项目;航空科学基金资助项目;江苏省产学研联合创新资金前瞻性研究项目

Network on chip mapping algorithm optimized for testing

ZHANG Ying,WU Yu,GE Fen   

  1. College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing Jiangsu 210016, China
  • Received:2014-05-19 Revised:2014-07-08 Online:2014-12-01 Published:2014-12-31
  • Contact: ZHANG Ying

摘要:

针对复杂片上系统(SoC)芯片的片上网络(NoC)映射方案未考虑测试需求的问题,提出了一种面向测试优化的NoC映射算法,兼顾了可测性的提升和映射开销的最小化。该映射方案首先依据特定的测试结构,使用划分算法进行片上系统所有IP核的测试分组,其优化目标为测试时间最短;之后,再基于分组内IP核之间的通信量,应用遗传算法实现NoC映射,其优化目标是在测试优化的基础上实现映射开销最小。通过多个ITC'02测试基准电路进行的实验结果表明:应用该方案后,测试时间平均减少12.67%;与随机任务映射相比,映射代价平均减少24.5%。

Abstract:

The problem of NoC (Network on Chip) mapping for complex SoC (System on Chip) chip is urgently needed to be solved while most of the existing mapping schemes do not considered testing requirements. This paper proposed a novel NoC mapping algorithm optimized for testing, which considered the improvement of testability and the minimization of mapping cost together. Firstly, the partition algorithm was adopted to arrange all the IP cores into parallel testing groups, combined with the optimized test structure, so that the testing time was minimized. Then, based on traffic information between IP cores, genetic algorithm was applied to accomplish the NoC mapping, which was aimed to the minimum mapping cost. The experimental results on ITC02 benchmark circuits show that the testing time can be reduced by 12.67% on average and the mapping costs decreased by 24.5% on average compared with the random mapping.

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