The problem of NoC (Network on Chip) mapping for complex SoC (System on Chip) chip is urgently needed to be solved while most of the existing mapping schemes do not considered testing requirements. This paper proposed a novel NoC mapping algorithm optimized for testing, which considered the improvement of testability and the minimization of mapping cost together. Firstly, the partition algorithm was adopted to arrange all the IP cores into parallel testing groups, combined with the optimized test structure, so that the testing time was minimized. Then, based on traffic information between IP cores, genetic algorithm was applied to accomplish the NoC mapping, which was aimed to the minimum mapping cost. The experimental results on ITC02 benchmark circuits show that the testing time can be reduced by 12.67% on average and the mapping costs decreased by 24.5% on average compared with the random mapping.
［1］BJERREGAARD T, MAHADEVAN S A. Survey of research and practices of network on chip［J］. ACM Computing Surveys, 2006, 38(1): 1-51.
［2］YANG S, LI L, GAO M, et al. An energy-and delay-aware mapping method of NoC［J］. Acta Electronica Sinica, 2008, 36(5): 937-942. (杨盛光, 李丽, 高明伦, 等. 面向能耗和延时的NoC映射方法［J］. 电子学报, 2008, 36(5): 937-942.)
［3］MANDELLI M, OST L, CARARA E, et al. Energy-aware dynamic task mapping for NoC-based MPSoCs［C］// Proceedings of 2011 IEEE International Symposium on Circuits and Systems (ISCAS). Piscataway: IEEE, 2011: 1676-1679.
［4］SEPULVEDA J, STRUM M, WANG J C, et al. A multi-objective approach for multi-application NoC mapping［C］// Proceedings of 2011 IEEE Second Latin American Symposium on Circuits and Systems. Piscataway: IEEE, 2011: 1-4.
［5］WANG L, LING X. Energy-and latency-aware NoC mapping based on chaos discrete particle swarm optimization［C］// Proceedings of the 5th IEEE International Conference on Communications and Mobile Computing. Piscataway: IEEE, 2010: 263-268.
［6］CHAKRABARTY K. Optimal test access architectures for system-on-a-chip［J］. ACM Transactions on Design Automation of Electronic Systems, 2001, 6(1): 26-49.
［7］AMORY A M, FERLINI F, LUBASZEWSKI M, et al. DFT for the reuse of Networks-on-Chip as test access mechanism［C］// Proceedings of the 25th IEEE VLSI Test Symposium. Piscataway: IEEE, 2007: 435-440.
［8］AGRAWAL M, RICHTER M, CHAKRABARTY K. A dynamic programming solution for optimizing test delivery in multicore SOCs［C］// Proceedings of the 2012 IEEE International Test Conference. Washington, DC: IEEE Computer Society, 2012:1-10.
［9］TAYAN O. Networks-on-Chip: challenges, trends and mechanisms for enhancements［C］// Proceedings of the 2009 International Conference on Information and Communication Technologies. Piscataway: IEEE, 2009: 57-62.
［10］ZHANG Y, WU N, GE F. The co-design of test structure and test data transfer mode for 2D-Mesh NoC［C/OL］.[2014-06-20](2013-10-20).http://www.engineeringvillage.com/search/doc/detailed.url?pageType=quickSearch&CID=quickSearchDetailedFormat&SEARCHID=9a181d16M83acM4d3fMb62fMf5264248f3ed&DOCINDEX=1&docid=null&database=1&displayPagination=yes&format=quickSearchDetailedFormat&dedupResultCount=null.
［11］MARINISSEN E J, IYENGAR V, CHAKRABARTY K. A set of benchmarks for modular testing of SOCs［C］// Proceedings of the 2002 International Test Conference. Washington, DC: IEEE Computer Society, 2002:519-528.
［12］LIU C S, SHI J, COTA E, et al. Power-aware test scheduling in Network-on-Chip using variable-rate on-chip clocking［C］// Proceedings of the 23rd IEEE VLSI Test Symposium. Piscataway: IEEE, 2005:349-354.
［13］HU J, MARCULESCU R. Energy-aware mapping for tile-based NoC architectures under performance constraints［C］// Proceedings of Asia and South Pacific Design Automation Conference. New York: ACM, 2003:233-239.
［14］DICK R P, RHODES D L, WOLF W. TGFF: task graphs for free［C］// Proceedings of the 6th International Workshop on Hardware/Software Codesign. Piscataway: IEEE, 1998:97-101.
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