关键词: 1553B总线, 通信终端, 可编程逻辑门阵列, 知识产权核, 可靠性

Abstract:

To meet the needs of ground simulation equipment used for spacecraft, a design of 1553B bus communication terminal Intellectual Property (IP) core based on Field Programmable Gate Array (FPGA) was proposed. On the premise of reliability, the bus system was designed with top-down approach and "two-process" coding method to generate object code with Very-High-Speed Integrated Circuit Hardware Description Language (VHDL), and then was simulated with ModelSim software, and finally, got verified and applied on actual device. The working mode of IP core can be configured with bus controller, remote terminal and bus monitor respectively. In addition, the IP core is easy to be integrated into System on Chip (SoC), and provides more choices for the further application of 1553B bus.

Key words: 1553B Bus, Communication Terminal, Field Programmable Gate Array, IP Core, Reliability