关键词: Y型双并行阵列结构, 现场可编程门阵列, 基2^2快速傅里叶变换, 多路径延迟交叉结构流水线, 蝶形运算

Abstract: A design and implementation method of Field Programmable Gate Array (FPGA) hardware structure optimization for Radix 22 Fast Fourier Transformation (R22FFT) algorithm is proposed to solve the problem that the Fast Fourier Transformation (FFT) algorithm requires a lot of resources and time to process large-scale data and thus leading to low operation speed. In the method, a Y-shaped dual parallel array structure for R22FFT algorithm is firstly constructed by combining a sequence conversion function and a pipeline structure, which reduces the number of hardware multipliers and increases the throughput of hardware structure effectively to improve the operation speed of FFT algorithm on FPGA. And then, the correlation characteristics of the twiddle factors are adopted in the single-stage operation of the R22FFT pipeline to optimize the on-chip storage resource consumption and reduced storage space by about 50.00%.. Finally, the scalability of hardware structure is further improved in realizing multi-point expansion such as points and points after the optimization of the N-point R22FFT algorithm structure has been completed. Furthermore, Verilog HDL language and Modelsim are utilized to implement hardware design and simulation, respectively. Then, the proposed method was synthesized and routed by using Vivado2018.3 software, and finally the performance analysis was carried out. The experimental results show that, compared with the four improved FFT hardware implementation methods, the operation time of the proposed method is reduced by 75.10%, 95.34%, 38.49% and 49.20%, respectively, which significantly improves the operation speed. At the same time, the resource consumption of the proposed method is reasonable and the consumption proportion is low. And it has the characteristics of low power consumption and strong scalability.

Key words: Y-shaped dual parallel array structure, Field Programmable Gate Array &#40, FPGA&#41, Radix 2^2 Fast Fourier Transformation &#40