Abstract: In the motion detection system, fast and efficient image segmentation is an essential part. Otsu method is a common and efficient image segmentation algorithm, and has been used in many various real-time systems. To meet the requirements of real-time systems, an implementation on FPGA of Altera's Cyclone II series for the BCVC (Between Class Variance Computation) of Otsu’s method is presented. It uses Verilog language to modeling and simulates in QuartusⅡ platform. Experimental results show that the design can obtain threshold quickly and effectively, and can effectively protects the fuzzy goals.

Key words: motion detection system, image segmentation, Otsu, FPGA

摘要： 在运动检测系统中，快速有效的图像分割是必不可少的一个环节。最大类间方差法是一种常用而有效的图像分割算法，并已在许多实时系统中采用。为满足系统对实时性的要求，采用Altera公司的Cyclone II 系列的FPGA实现最大类间方差算法。采用Verilog语言对算法实现建模，并在Quartus Ⅱ平台进行了仿真验证。实验结果表明，该设计能够快速有效的得到阈值，并能有效保护模糊目标的作用。

关键词: 运动检测系统, 图像分割, 最大类间方差, FPGA