计算机应用 ›› 2013, Vol. 33 ›› Issue (06): 1544-1547.DOI: 10.3724/SP.J.1087.2013.01544

• 先进计算 • 上一篇    下一篇

面向异构多核处理器的并行代价模型

黄品丰1,2,赵荣彩1,2,姚远1,2,赵捷1,2   

  1. 1. 数字工程与先进计算国家重点实验室,郑州 450002
    2. 信息工程大学,郑州 450002
  • 收稿日期:2012-12-11 修回日期:2013-01-08 出版日期:2013-06-01 发布日期:2013-06-05
  • 通讯作者: 黄品丰
  • 作者简介:黄品丰(1987-),男,广东信宜人,硕士研究生,主要研究方向:并行编译; 赵荣彩(1957-),男,河南洛阳人,教授,博士生导师,CCF会员,主要研究方向:高性能计算、并行编译;姚远(1972-),男,河南郑州人,教授,博士,主要研究方向:先进编译;赵捷(1987-),男,内蒙古通辽人,博士研究生,主要研究方向:先进编译。
  • 基金资助:

    国家“核高基”重大专项(2009ZX01036-001-001-2)

Parallel cost model for heterogeneous multi-core processors

HUANG Pinfeng1,2,ZHAO Rongcai1,2,YAO Yuan1,2,ZHAO Jie1,2   

  1. 1. Information Engineering University, Zhengzhou Henan 450002, China
    2. State Key Laboratory of Mathematical Engineering and Advanced Computing, Zhengzhou Henan 450002, China
  • Received:2012-12-11 Revised:2013-01-08 Online:2013-06-05 Published:2013-06-01
  • Contact: HUANG Pinfeng

摘要: 现有的并行代价模型大多是面向共享存储或分布存储结构设计的,不完全适合异构多核处理器。为解决这个问题,提出了面向异构多核处理器的并行代价模型,通过定量刻画计算核心运算能力、存储访问延迟和数据传输开销对循环并行执行时间的影响,提高加速并行循环识别的准确性。实验结果表明,提出的并行代价模型能有效识别加速并行循环,将其识别结果作为后端生成并行代码的依据,可有效提高并行程序在异构多核处理器上的性能。

关键词: 自动并行化, 并行代价模型, 异构多核, 数据传输开销, 加速并行循环

Abstract: The existing parallel cost models are mostly devised for shared memory or distributed memory architecture, thus not suitable for heterogeneous multi-core processors. In order to solve the problem, a new parallel cost model for heterogeneous multi-cores was proposed. It described the impact of computing capacity, memory access delay and data transfer cost on parallel execution time of loops quantitatively, thus improving the veracity of accelerated parallel loop recognition. The experimental results show that the proposed model can effectively recognize the accelerated parallel loops. Using its recognition results to generate parallel codes can improve the performance of parallel programs on heterogeneous multi-core processors significantly.

Key words: auto-parallelization, parallel cost model, heterogeneous multi-core, data transfer cost, accelerated parallel loop

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