1. College of Physics and Microelectronics, Hunan University, Changsha Hunan 410082, China;
2. Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
In order to adapt to the the requirement of the Instruction Set Simulator (ISS) simulation speed in embedded system development, an improved ISS technology was put forward.The technology introduced instruction preprocessing, dynamic decode cache structure, multi-thread C function generation and dynamic scheduling technique based on the existing static multi-core simulator to achieve the optimization of the simulator performance. This technique has been applied successfully in forming OPT-ISS, which is based on IME-Diamond multi-core DSP processor. The experimental results show that this technique improves the simulation speed indeed.
付琳, 胡锦, 梁利平. 指令集仿真器的关键技术[J]. 计算机应用, 2015, 35(5): 1421-1425.
FU Lin, HU Jin, LIANG Liping. Key techniques for fast instruction set simulator. Journal of Computer Applications, 2015, 35(5): 1421-1425.
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2015, Vol. 35 
